公开(公告)号：US20240128223A1

公开(公告)日：2024-04-18

申请号：US18399220

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L24/20 ,  H01L23/3157 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L2924/3511 ,  H01L2924/381

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US20180286799A1

公开(公告)日：2018-10-04

申请号：US15997555

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Thorsten MEYER ,  Gerald OFNER ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Sven ALBERS ,  Christian GEISSLER

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/15151 ,  H01L2924/15159 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US20200373259A1

公开(公告)日：2020-11-26

申请号：US16421315

申请日：2019-05-23

Applicant: Intel Corporation

Inventor： Sonja KOLLER ,  Kilian ROTH ,  Josef HAGN ,  Andreas WOLTER ,  Andreas AUGUSTIN

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01P3/00 ,  H01P11/00 ,  H01Q1/22

Abstract: Embodiments include semiconductor packages and methods of forming the semiconductor packages. A semiconductor package includes a die over a substrate, a first conductive layer over the die, and a conductive cavity antenna over the first conductive layer and substrate. The conductive cavity antenna includes a conductive cavity, a cavity region, and a plurality of interconnects. The conductive cavity is over the first conductive layer and surrounds the cavity region. The semiconductor package also includes a second conductive layer over the conductive cavity antenna, first conductive layer, and substrate. The conductive cavity extends vertically from the first conductive layer to the second conductive layer. The cavity region may be embedded with the conductive cavity, the first conductive layer, and the second conductive layer. The plurality of interconnects may include first, second, and third interconnects. The first interconnects may include through-mold vias (TMVs), through-silicon vias (TSVs), conductive sidewalls, or conductive trenches.

公开(公告)号：US20160358897A1

公开(公告)日：2016-12-08

申请号：US14778036

申请日：2014-12-09

Applicant: INTEL CORPORATION

Inventor： Sven ALBERS ,  Andreas WOLTER ,  Klaus REINGRUBER ,  Thorsten MEYER

IPC: H01L25/16 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L49/02 ,  H01L21/683

CPC classification number: H01L25/16 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/552 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/50 ,  H01L28/00 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81201 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

Abstract translation: 一种方法，包括通过积聚过程在衬底上形成至少一个被动结构; 在衬底上引入一个或多个集成电路芯片; 以及在所述至少一个无源结构和所述一个或多个集成电路芯片上引入模塑料。 一种方法，包括通过三维印刷方法在基板上形成至少一个被动结构; 在衬底上引入一个或多个集成电路芯片; 以及将所述至少一个被动结构和所述一个或多个集成电路芯片嵌入到模塑料中。 一种包括包括至少一个三维印刷无源结构和嵌入在成型材料中的一个或多个集成电路芯片的封装基板的装置。

公开(公告)号：US20240213225A1

公开(公告)日：2024-06-27

申请号：US18601774

申请日：2024-03-11

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20220199562A1

公开(公告)日：2022-06-23

申请号：US17131663

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Bernd WAIDHAS ,  Andreas WOLTER ,  Georg SEIDEMANN ,  Thomas WAGNER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.

公开(公告)号：US20220108976A1

公开(公告)日：2022-04-07

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.