公开(公告)号：US09977075B1

公开(公告)日：2018-05-22

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G06Q10/06 ,  G06Q10/08 ,  G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US20160378151A1

公开(公告)日：2016-12-29

申请号：US14752826

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Mark A. Schmisseur ,  Raj K. Ramanujan ,  Mohamed Arafa ,  Christopher F. Connor ,  Sudeep Puligundla ,  Mohan J. Kumar

IPC: G06F1/26 ,  G06F3/06

CPC classification number: G06F3/0685 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688

Abstract: Methods and apparatus related to Rack Scale Architecture (RSA) and/or Shared Memory Controller (SMC) techniques of fast zeroing are described. In one embodiment, a storage device stores meta data corresponding to a portion of a non-volatile memory. Logic, coupled to the non-volatile memory, causes an update to the stored meta data in response to a request for initialization of the portion of the non-volatile memory. The logic causes initialization of the portion of the non-volatile memory prior to a reboot or power cycle of the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与快速归零的机架规模架构（RSA）和/或共享存储器控制器（SMC）技术相关的方法和装置。 在一个实施例中，存储设备存储对应于非易失性存储器的一部分的元数据。 耦合到非易失性存储器的逻辑响应于对非易失性存储器的该部分的初始化的请求而对存储的元数据进行更新。 在非易失性存储器的重新启动或重新启动之前，该逻辑导致非易失性存储器的该部分的初始化。 还公开并要求保护其他实施例。

公开(公告)号：US10163502B2

公开(公告)日：2018-12-25

申请号：US15396251

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Hanmant P. Belgal

IPC: G06F3/06 ,  G11C13/00

Abstract: In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.

公开(公告)号：US20180143242A1

公开(公告)日：2018-05-24

申请号：US15360899

申请日：2016-11-23

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Rahul Khanna

IPC: G01R31/28 ,  G06F17/50

CPC classification number: G01R31/2851 ,  G01R31/2855 ,  G06F17/5036

Abstract: Embodiments detailed herein include an apparatus that includes a reliability assessment engine (RAE) stored in non-volatile memory and processing circuitry to execute the RAE to: receive data of at least one physical condition from a plurality of intra-die variation monitoring circuits, apply the received data least one to at least one reliability physics model, and calculate at least one of an estimated amount of lifetime consumed and an estimated amount of lifetime remaining.

公开(公告)号：US09691492B1

公开(公告)日：2017-06-27

申请号：US15280669

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Zion S. Kwok ,  Christopher F. Connor ,  Philip Hillier ,  Jeffrey W. Ryden

IPC: G11C5/14 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/28 ,  G11C16/10 ,  G11C16/20 ,  G11C16/30

Abstract: A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device.

公开(公告)号：US20170160338A1

公开(公告)日：2017-06-08

申请号：US14961824

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Christopher F. Connor ,  Bruce Querbach ,  Gordon McFadden ,  Hanmant P. Belgal ,  Rahul Khanna

IPC: G01R31/28 ,  G11C29/00 ,  G11C7/00

CPC classification number: G01R31/2894 ,  G11C5/04 ,  G11C7/00 ,  G11C16/3495 ,  G11C29/025 ,  G11C29/16 ,  G11C29/40 ,  G11C29/50016 ,  G11C2029/5004

Abstract: In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a reliability physics module stored in non-volatile memory and compute logic to calculate at least one of an estimated amount of lifetime consumed or an estimated amount of lifetime remaining after a period of operation of an integrated circuit. In embodiments, the calculation may be based at least in part on the reliability physics model and data of at least one physical condition of the integrated circuit sensed during or at the end of the period of operation. Other embodiments may be described and/or claimed.