公开(公告)号：US09997457B2

公开(公告)日：2018-06-12

申请号：US14137526

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L23/53209 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76879 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/4966 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US10546772B2

公开(公告)日：2020-01-28

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Richard E. Schenker ,  Hui Jae Yoo ,  Kevin L. Lin ,  Jasmeet S. Chawla ,  Stephanie A. Bojarski ,  Satyarth Suri ,  Colin T. Carver ,  Sudipto Naskar

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US09165824B2

公开(公告)日：2015-10-20

申请号：US14039893

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Christopher Jezewski ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.

Abstract translation: 包括全覆层互连的金属化层和形成完全包层的互连的方法。 在电介质层中形成开口，其中介电层具有表面，并且开口包括壁和底部。 扩散阻挡层和粘合层沉积在介电层上。 互连材料沉积在介电层上并回流到形成互连的开口中。 在互连上沉积粘合覆盖层和扩散阻挡覆盖层。 互连被粘合层和粘合覆盖层包围，粘合层和粘合覆盖层被扩散阻挡层和扩散覆盖层包围。

公开(公告)号：US11594452B2

公开(公告)日：2023-02-28

申请号：US17122939

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US10896847B2

公开(公告)日：2021-01-19

申请号：US16539957

申请日：2019-08-13

Applicant: Intel Corporation

Inventor： Il-Seok Son ,  Colin T. Carver ,  Paul B. Fischer ,  Patrick Morrow ,  Kimin Jun

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/84 ,  H01L21/306 ,  H01L25/065 ,  H01L27/088 ,  H01L29/06

Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.

公开(公告)号：US10700007B2

公开(公告)日：2020-06-30

申请号：US15925009

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US11328993B2

公开(公告)日：2022-05-10

申请号：US16881530

申请日：2020-05-22

Applicant: Intel Corporation

Inventor： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US09385085B2

公开(公告)日：2016-07-05

申请号：US14855792

申请日：2015-09-16

Applicant: INTEL CORPORATION

Inventor： Manish Chandhok ,  Hui Jae Yoo ,  Christopher J. Jezewski ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/5283 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein the dielectric layer has a surface and the opening includes walls and a bottom. A diffusion barrier layer and an adhesion layer are deposited on the dielectric layer. An interconnect material is deposited on the dielectric layer and reflowed into the opening forming an interconnect. An adhesion capping layer and diffusion barrier capping layer are deposited over the interconnect. The interconnect is surrounded by the adhesion layer and the adhesion capping layer and the adhesion layer and the adhesion capping layer are surrounded by the diffusion barrier layer and the diffusion capping layer.