公开(公告)号：US20200066595A1

公开(公告)日：2020-02-27

申请号：US16465490

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  CHYTRA PAWASHE ,  ANAND S. MURTHY ,  DANIEL PANTUSO ,  TAHIR GHANI

IPC: H01L21/8234 ,  H01L29/06 ,  H01L27/088

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

公开(公告)号：US20190341464A1

公开(公告)日：2019-11-07

申请号：US16416445

申请日：2019-05-20

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/45 ,  H01L29/165 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US20190341300A1

公开(公告)日：2019-11-07

申请号：US16473960

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.

公开(公告)号：US20180108750A1

公开(公告)日：2018-04-19

申请号：US15573168

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  HEI KAM ,  TAHIR GHANI ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8256 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

公开(公告)号：US20160329431A1

公开(公告)日：2016-11-10

申请号：US15212991

申请日：2016-07-18

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/786 ,  H01L21/768 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/78618 ,  H01L21/76805 ,  H01L21/76886 ,  H01L21/76895 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

公开(公告)号：US20200381549A1

公开(公告)日：2020-12-03

申请号：US16998382

申请日：2020-08-20

Applicant: INTEL CORPORATION

Inventor： STEPHEN M. CEA ,  ROZA KOTLYAR ,  HAROLD W. KENNEL ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  WILLY RACHMADY ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161

Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based NMOS transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, a germanium or silicon germanium film is cladded onto silicon fins in order to provide a desired tensile strain in the core of the fin, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and cladding deposition can occur at a plurality of locations within typical process flow. In various embodiments, fins may be formed with a minimum width (or later thinned) so as to improve transistor performance. In some embodiments, a thinned fin also increases tensile strain across the core of a cladded fin. In some cases, strain in the core may be further enhanced by adding an embedded silicon epitaxial source and drain.

公开(公告)号：US20190259835A1

公开(公告)日：2019-08-22

申请号：US16402739

申请日：2019-05-03

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L21/3215 ,  H01L27/092 ,  H01L29/417 ,  H01L23/535 ,  H01L29/78 ,  H01L29/45 ,  H01L29/36 ,  H01L21/02 ,  H01L29/167 ,  H01L29/49 ,  H01L29/165 ,  H01L29/778

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

公开(公告)号：US20180358440A1

公开(公告)日：2018-12-13

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

公开(公告)号：US20180019170A1

公开(公告)日：2018-01-18

申请号：US15668288

申请日：2017-08-03

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  DANIEL B. AUBERTINE ,  ANAND S. MURTHY ,  GAURAV THAREJA ,  TAHIR GHANI

IPC: H01L21/8238 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.