公开(公告)号：US12067428B2

公开(公告)日：2024-08-20

申请号：US17128525

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Stav Gurtovoy ,  Mateusz Maria Przybylski ,  Michael Apodaca ,  Manjunath D S

IPC: G06F9/52 ,  G06F9/48 ,  G06T1/20

CPC classification number: G06F9/52 ,  G06F9/4881 ,  G06F9/522 ,  G06T1/20

Abstract: An apparatus to facilitate thread synchronization is disclosed. The apparatus comprises one or more processors to execute a producer thread to generate a plurality of commands, execute a consumer thread to process the plurality of commands and synchronize the producer thread with the consumer thread, including updating a producer fence value upon generation of in-order commands, updating a consumer fence value upon processing of the in-order commands and performing a synchronization operation based on the consumer fence value, wherein the producer fence value and the consumer fence value each correspond to an order position of an in-order command.

公开(公告)号：US20240134527A1

公开(公告)日：2024-04-25

申请号：US17971290

申请日：2022-10-20

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Michael Apodaca ,  Yoav Harel ,  Guei-Yuan Lueh ,  John A. Wiegert

IPC: G06F3/06 ,  G06T1/60

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06T1/60

Abstract: Embodiments described herein provide a technique to enable access to entries in a surface state or sampler state using 64-bit virtual addresses. One embodiment provides a graphics core that includes memory access circuitry configured to facilitate access to the memory by functional units of the graphics core. The memory access circuitry is configured to receive a message to access an entry in a surface state or a sampler state associated with a parallel processing operation. The message specifies a base address for a surface state entry or sampler state entry. The circuitry can add the base address and the offset to determine a 64-bit virtual address for the entry in the surface state entry or the sampler state and submit a memory access request to the memory to access the entry of the surface state or sampler state.

公开(公告)号：US11710269B2

公开(公告)日：2023-07-25

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Zack Waters ,  Michael Apodaca ,  Daniel Johnston ,  Jason Surprise ,  Prasoonkumar Surti ,  Subramaniam Maiyuran ,  Peter Doyle ,  Saurabh Sharma ,  Ankur Shah ,  Murali Ramadoss

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

CPC classification number: G06T15/005 ,  G06T15/40 ,  G06T15/80 ,  G06T2210/52

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US11663774B2

公开(公告)日：2023-05-30

申请号：US17684686

申请日：2022-03-02

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T15/50 ,  G06T15/00 ,  G06T15/80 ,  G06T17/20

CPC classification number: G06T15/503 ,  G06T15/005 ,  G06T15/80 ,  G06T17/205 ,  G06T2200/12

Abstract: Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems, apparatuses and methods may provide a way to perform anti-aliasing at the edges of the object based on a coarse pixel rate, where the coarse pixels may be based on a coarse Z value indicate a resolution or granularity of detail of the coarse pixel. The systems, apparatuses and methods may use a shader dispatch engine to dispatch raster rules to a pixel shader to direct the pixel shader to include, in a tile and/or tessellation triangle, one more finer coarse pixels based on a percent of coverage provided by a finer coarse pixel of a tessellation triangle at or along the edge of the object.

公开(公告)号：US20230140640A1

公开(公告)日：2023-05-04

申请号：US17518328

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Stav Gurtovoy ,  Abhishek Venkatesh ,  Michael Apodaca ,  Travis Schluessler ,  John Feit

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: Methods, systems and apparatuses may provide for technology that marks a graphics resource as a flush candidate during a current frame, conducts an early flush of a command buffer from the graphics resource if a write event is detected with respect to the graphics resource during a subsequent frame, and bypasses the early flush if the write event is not detected with respect to the graphics resource during the subsequent frame. In one example, the graphics resource is marked as the flush candidate in response to a read back operation of the host processor with respect to the graphics resource, wherein the read back operation retrieves a query result and/or maps a staging resource.

公开(公告)号：US11520555B2

公开(公告)日：2022-12-06

申请号：US17162864

申请日：2021-01-29

Applicant: Intel Corporation

Inventor： Deepak S. Vembar ,  Atsuo Kuwahara ,  Chandrasekaran Sakthivel ,  Radhakrishnan Venkataraman ,  Brent E. Insko ,  Anupreet S. Kalra ,  Hugues Labbe ,  Altug Koker ,  Michael Apodaca ,  Kai Xiao ,  Jeffery S. Boles ,  Adam T. Lake ,  David M. Cimini ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Ankur N. Shah ,  Abhishek R. Appu ,  Joydeep Ray ,  Wenyin Fu ,  Nikos Kaburlasos ,  Prasoonkumar Surti ,  Bhushan M. Borole

IPC: G06F3/14 ,  G06F3/147 ,  G06T1/20 ,  G09G5/36 ,  H04L65/402 ,  G09G3/00 ,  H04L67/131

Abstract: An embodiment of a graphics apparatus may include a processor, memory communicatively coupled to the processor, and a collaboration engine communicatively coupled to the processor to identify a shared graphics component between two or more users in an environment, and share the shared graphics components with the two or more users in the environment. Embodiments of the collaboration engine may include one or more of a centralized sharer, a depth sharer, a shared preprocessor, a multi-port graphics subsystem, and a decode sharer. Other embodiments are disclosed and claimed.

公开(公告)号：US20220172316A1

公开(公告)日：2022-06-02

申请号：US17486330

申请日：2021-09-27

Applicant: Intel Corporation

Inventor： Abhishek Venkatesh ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06T15/00

Abstract: An embodiment of a graphics command coordinator apparatus may include a commonality identifier to identify a commonality between a first graphics command corresponding to a first frame and a second graphics command corresponding to a second frame, a commonality analyzer communicatively coupled to the commonality identifier to determine if the first graphics command and the second graphics command can be processed together based on the commonality identified by the commonality identifier, and a commonality indicator communicatively coupled to the commonality analyzer to provide an indication that the first graphics command and the second graphics command are to be processed together. Other embodiments are disclosed and claimed.

公开(公告)号：US11257182B2

公开(公告)日：2022-02-22

申请号：US16943984

申请日：2020-07-30

Applicant: Intel Corporation

Inventor： John Gierach ,  Abhishek Venkatesh ,  Travis Schluessler ,  Devan Burke ,  Tomer Bar-On ,  Michael Apodaca

IPC: G06T1/20 ,  G06T17/10

Abstract: Embodiments are generally directed to GPU mixed primitive topology type processing. An embodiment of an apparatus includes one or more processor cores; and a memory to store data for graphics processing, wherein the one or more processing cores are to generate in the memory a vertex buffer to store vertex data for a mesh to be rendered and an index buffer to index the vertex data stored in the vertex buffer, the index buffer being structured to include index data for multiple primitive topology types. The one or more processor cores are to process the index data for the plurality of primitive topology types from the index buffer and fetch vertex data from the vertex buffer; and are to set up each primitive topology type of the plurality of primitive topology types for processing in a single draw operation.

公开(公告)号：US11244479B2

公开(公告)日：2022-02-08

申请号：US16919839

申请日：2020-07-02

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11030713B2

公开(公告)日：2021-06-08

申请号：US15483829

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T1/60 ,  G06T9/00 ,  H04N19/503 ,  H04N19/436

Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.