公开(公告)号：US20240014149A1

公开(公告)日：2024-01-11

申请号：US18372533

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Thomas SOUNART ,  Kristof DARMAWIKARTA ,  Henning BRAUNISCH ,  Prithwish CHATTERJEE ,  Andrew J. BROWN

IPC: H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/642 ,  H01L23/49894 ,  H01L23/49838 ,  H01L24/16 ,  H01L23/49827 ,  H01L21/4846 ,  H01L2224/16265 ,  H01L2224/16225 ,  H01L2924/19103 ,  H01L2924/19041

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US20200006005A1

公开(公告)日：2020-01-02

申请号：US16024715

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Rahul JAIN ,  Andrew J. BROWN ,  Prithwish CHATTERJEE ,  Sai VADLAMANI ,  Lauren LINK

IPC: H01G4/33 ,  H01L49/02 ,  H01L23/522

Abstract: Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

公开(公告)号：US20200006211A1

公开(公告)日：2020-01-02

申请号：US16019996

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Andrew J. BROWN ,  Lauren A. LINK ,  Sai VADLAMANI ,  Prithwish CHATTERJEE ,  Lisa CHEN

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18 ,  H05K1/03 ,  D06M11/81 ,  D06B3/10 ,  D03D1/00 ,  D03D15/00 ,  B32B5/26 ,  B32B5/02 ,  B32B7/12

Abstract: Apparatuses, systems and methods associated with substrate assemblies for computer devices are disclosed herein. In embodiments, a core for a substrate assembly includes a first metal region, a second metal region, and a dielectric region located between the first metal region and the second metal region. The dielectric region includes one or more fibers, wherein each of the one or more fibers includes aluminum, boron, silicon, or oxide. Other embodiments may be described and/or claimed.

公开(公告)号：US20190279806A1

公开(公告)日：2019-09-12

申请号：US15919066

申请日：2018-03-12

Applicant: Intel Corporation

Inventor： Kristof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Sandeep GAAN ,  Sri Ranga Sai BOYAPATI ,  Prithwish CHATTERJEE ,  Sameer PAITAL ,  Rahul JAIN ,  Junnan ZHAO

IPC: H01F27/28 ,  H01F27/24 ,  H01F41/04

Abstract: Embodiments include inductors and methods of forming inductors. In an embodiment, an inductor may include a substrate core and a conductive through-hole through the substrate core. Embodiments may also include a magnetic sheath around the conductive through hole. In an embodiment, the magnetic sheath is separated from the plated through hole by a barrier layer. In an embodiment, the barrier layer is formed over an inner surface of the magnetic sheath and over first and second surfaces of the magnetic sheath.

公开(公告)号：US20210134727A1

公开(公告)日：2021-05-06

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai BOYAPATI ,  Kristof DARMAWIKARTA ,  Hiroki TANAKA ,  Srinivas V. PIETAMBARAM ,  Frank TRUONG ,  Praneeth AKKINEPALLY ,  Andrew J. BROWN ,  Lauren A. LINK ,  Prithwish CHATTERJEE

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US20190295967A1

公开(公告)日：2019-09-26

申请号：US15933599

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kirstof DARMAWIKARTA ,  Srinivas PIETAMBARAM ,  Prithwish CHATTERJEE ,  Sri Ranga Sai BOYAPATI ,  Wei Lun JEN

IPC: H01L23/64 ,  H01F41/04 ,  H01F27/28 ,  H01F1/14 ,  H01F1/34 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.