公开(公告)号：US20220328431A1

公开(公告)日：2022-10-13

申请号：US17852003

申请日：2022-06-28

申请人： Intel Corporation

发明人： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

摘要： Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.

公开(公告)号：US20220187548A1

公开(公告)日：2022-06-16

申请号：US17122340

申请日：2020-12-15

申请人： Intel Corporation

发明人： Brandon C. MARIN ,  Divya PRATAP ,  Hiroki TANAKA ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Srinivas V. PIETAMBARAM ,  Xiaoqian LI ,  Sai VADLAMANI ,  Jeremy ECTON

IPC分类号： G02B6/42 ,  G02F1/01 ,  G02F1/09

摘要： Embodiments disclosed herein include optical systems with Faraday rotators in order to enhance efficiency. In an embodiment, a photonics package comprises an interposer and a patch over the interposer. In an embodiment, the patch overhangs an edge of the interposer. In an embodiment, the photonics package further comprises a photonics die on the patch and a Faraday rotator passing through a thickness of the patch. In an embodiment, the Faraday rotator is below the photonics die.

公开(公告)号：US20220155539A1

公开(公告)日：2022-05-19

申请号：US16953146

申请日：2020-11-19

申请人： Intel Corporation

发明人： Srinivas V. PIETAMBARAM ,  Brandon C. MARIN ,  Sameer PAITAL ,  Sai VADLAMANI ,  Rahul N. MANEPALLI ,  Xiaoqian LI ,  Suresh V. POTHUKUCHI ,  Sujit SHARAN ,  Arnab SARKAR ,  Omkar KARHADE ,  Nitin DESHPANDE ,  Divya PRATAP ,  Jeremy ECTON ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Zhichao ZHANG ,  Kemal AYGÜN ,  Bai NIE ,  Kristof DARMAWIKARTA ,  James E. JAUSSI ,  Jason M. GAMBA ,  Bryan K. CASPER ,  Gang DUAN ,  Rajesh INTI ,  Mozhgan MANSURI ,  Susheel JADHAV ,  Kenneth BROWN ,  Ankar AGRAWAL ,  Priyanka DOBRIYAL

IPC分类号： G02B6/42

摘要： Embodiments disclosed herein include optical packages. In an embodiment, an optical package comprises a package substrate, and a photonics die coupled to the package substrate. In an embodiment, a compute die is coupled to the package substrate, where the photonics die is communicatively coupled to the compute die by a bridge in the package substrate. In an embodiment, the optical package further comprises an optical waveguide embedded in the package substrate. In an embodiment, a first end of the optical waveguide is below the photonics die, and a second end of the optical waveguide is substantially coplanar with an edge of the package substrate.

公开(公告)号：US20190355675A1

公开(公告)日：2019-11-21

申请号：US15982652

申请日：2018-05-17

申请人： Intel Corporation

发明人： Kyu-Oh LEE ,  Sai VADLAMANI ,  Rahul JAIN ,  Junnan ZHAO ,  Ji Yong PARK ,  Cheng XU ,  Seo Young KIM

IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

摘要： Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

公开(公告)号：US20230420396A1

公开(公告)日：2023-12-28

申请号：US18253954

申请日：2020-12-23

申请人： Intel Corporation

发明人： Tolga ACIKALIN ,  Arnaud AMADJIKPE ,  Brent R. CARLTON ,  Chia-Pin CHIU ,  Timothy F. COX ,  Kenneth P. FOUST ,  Bryce D. HORINE ,  Telesphor KAMGAING ,  Renzhi LIU ,  Jason A. MIX ,  Sai VADLAMANI ,  Tae Young YANG ,  Zhen ZHOU

IPC分类号： H01L23/66 ,  H01Q9/42 ,  H01Q1/22 ,  H01Q9/36 ,  H01Q21/24 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

CPC分类号： H01L23/66 ,  H01Q9/42 ,  H01Q1/2283 ,  H01Q9/36 ,  H01Q21/24 ,  H01L25/0652 ,  H01L2924/1421 ,  H01L24/16 ,  H01L23/5381 ,  H01L2223/6677 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L25/0655

摘要： In various aspects, a device-to-device communication system is provided including a first device and a second device. Each of the first device and the second device includes an antenna, a radio frequency frond-end circuit, and a baseband circuit. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a cover structure housing the first device and the second device. Each of the first device and the second device are at least one of a chiplet or a package. The device-to-device communication system further includes a radio frequency signal interface wirelessly communicatively coupling the first device and the second device. The radio frequency signal interface includes the first antenna and the second antenna.

公开(公告)号：US20220415770A1

公开(公告)日：2022-12-29

申请号：US17356046

申请日：2021-06-23

申请人： Intel Corporation

发明人： Omkar KARHADE ,  Sai VADLAMANI ,  Xavier F. BRUN ,  Hemanth DHAVALESWARAPU

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/528 ,  H01L21/50 ,  H01L33/62 ,  H01L31/02

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

公开(公告)号：US20200168569A1

公开(公告)日：2020-05-28

申请号：US16481385

申请日：2017-03-30

申请人： Intel Corporation

发明人： Sai VADLAMANI ,  Aleksandar ALEKSOV ,  Rahul JAIN ,  Kyu Oh LEE ,  Kristof Kuwawi DARMAWIKARTA ,  Robert Alan MAY ,  Sri Ranga Sai BOYAPATI ,  Telesphor KAMGAING

IPC分类号： H01L23/66 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

摘要： Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：US20200006005A1

公开(公告)日：2020-01-02

申请号：US16024715

申请日：2018-06-29

申请人： Intel Corporation

发明人： Rahul JAIN ,  Andrew J. BROWN ,  Prithwish CHATTERJEE ,  Sai VADLAMANI ,  Lauren LINK

IPC分类号： H01G4/33 ,  H01L49/02 ,  H01L23/522

摘要： Embodiments herein relate to systems, apparatuses, processing, and techniques related to patterning one or more sides of a thin film capacitor (TFC) sheet, where the TFC sheet has a first side and a second side opposite the first side. The first side and the second side of the TFC sheet are metal and are separated by a dielectric layer, and the patterned TFC sheet is to provide at least one of a capacitor or a routing feature on a first side of a substrate that has the first side and a second side opposite the first side.

公开(公告)号：US20240186202A1

公开(公告)日：2024-06-06

申请号：US18415268

申请日：2024-01-17

申请人： Intel Corporation

发明人： Rahul JAIN ,  Kyu Oh LEE ,  Siddharth K. ALUR ,  Wei-Lun K. JEN ,  Vipul V. MEHTA ,  Ashish DHALL ,  Sri Chaitra J. CHAVALI ,  Rahul N. MANEPALLI ,  Amruthavalli P. ALUR ,  Sai VADLAMANI

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/3185 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/53295 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/83051 ,  H01L2924/18161

摘要： An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：US20220367104A1

公开(公告)日：2022-11-17

申请号：US17873518

申请日：2022-07-26

申请人： Intel Corporation

发明人： Cheng XU ,  Kyu-Oh LEE ,  Junnan ZHAO ,  Rahul JAIN ,  Ji Yong PARK ,  Sai VADLAMANI ,  Seo Young KIM

IPC分类号： H01F27/28 ,  H01F27/02 ,  H01F27/24

摘要： Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.