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    TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY
    2.
    发明申请
    TECHNIQUES FOR FORMING LOGIC INCLUDING INTEGRATED SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY 审中-公开

    公开(公告)号：US20190081233A1

    公开(公告)日：2019-03-14

    申请号：US16073687

    申请日：2016-04-01

    Applicant: INTEL CORPORATION

    Inventor： KEVIN J. LEE ,  OLEG GOLONZKA ,  TAHIR GHANI ,  RUTH A. BRAIN ,  YIH WANG

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

    Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

    VIA BLOCKING LAYER
    3.
    发明申请
    VIA BLOCKING LAYER 审中-公开

    公开(公告)号：US20170330794A1

    公开(公告)日：2017-11-16

    申请号：US15528427

    申请日：2014-12-23

    Applicant: INTEL CORPORATION

    Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

    IPC: H01L21/768 ,  H01L23/31 ,  H01L23/528

    CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

    VIA BLOCKING LAYER
    4.
    发明申请
    VIA BLOCKING LAYER 审中-公开

    公开(公告)号：US20180174893A1

    公开(公告)日：2018-06-21

    申请号：US15898618

    申请日：2018-02-18

    Applicant: INTEL CORPORATION

    Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31

    Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

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