公开(公告)号：US20150162290A1

公开(公告)日：2015-06-11

申请号：US14625579

申请日：2015-02-18

Applicant: Intel Corporation

Inventor： KEVIN J. LEE

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/11001 ,  H01L2224/1183 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/81191 ,  H01L2224/81204 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/0665 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2224/11 ,  H01L2224/27 ,  H01L2224/11848 ,  H01L21/304

Abstract: A structure and method of handling a device wafer during through-silicon via (TSV) processing are described in which a device wafer is bonded to a temporary support substrate with a permanent thermosetting material. Upon removal of the temporary support substrate a planar frontside bonding surface including a reflowed solder bump and the permanent thermosetting material is exposed.

Abstract translation: 描述了在通硅（TSV）处理期间处理器件晶片的结构和方法，其中器件晶片通过永久性热固性材料结合到临时支撑衬底。 在移除临时支撑基板时，露出包括回流焊料凸块和永久性热固性材料的平面前沿接合表面。

公开(公告)号：US20170040255A1

公开(公告)日：2017-02-09

申请号：US15038623

申请日：2013-12-23

Applicant: Uwe ZILLMANN ,  Andre SCHAEFER ,  Ruchir SARASWAT ,  Guido DROEGE ,  Rinkle JAIN ,  Nicholas P. COWLEY ,  INTEL CORPORATION

Inventor： KEVIN J. LEE ,  RUCHIR SARASWAT ,  UWE ZILLMANN ,  NICHOLAS P. COWLEY ,  ANDRE SCHAEFER ,  RINKLE JAIN ,  GUIDO DROEGE

IPC: H01L23/522 ,  H01L21/822 ,  H01L23/492 ,  H01L21/48 ,  H01L27/06 ,  H01L23/498

CPC classification number: H01L23/5223 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/4875 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/481 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L25/0657 ,  H01L27/0629 ,  H01L28/90 ,  H01L2225/06544 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract translation: 公开了用于在半导体管芯中形成通孔通孔（TBV）隔离同轴电容器的技术。 在一些实施例中，使用所公开的技术提供的圆柱形电容器可以包括例如由介电材料和外导体板包围的导电TBV。 根据一些实施例，TBV和外板可以形成为例如以同轴布置彼此自对准。 所公开的电容器可以延伸穿过主模具的主体，使得其端子在其上表面和/或下表面上可接近。 因此，根据一些实施例，在一些情况下，主体管芯可以与另一个管芯电连接以提供管芯堆叠或其他三维集成电路（3D IC）。 在一些情况下，所公开的电容器可用于例如在开关电容器电压调节器（SCVR）中提供集成电容。

公开(公告)号：US20190081233A1

公开(公告)日：2019-03-14

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN J. LEE ,  OLEG GOLONZKA ,  TAHIR GHANI ,  RUTH A. BRAIN ,  YIH WANG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.