公开(公告)号：US20190386062A1

公开(公告)日：2019-12-19

申请号：US16464023

申请日：2016-12-27

Applicant: INTEL CORPORATION

Inventor： YIH WANG

IPC: H01L27/22 ,  H01L27/24 ,  G11C5/06 ,  H01L43/04 ,  H01L43/06 ,  H01L43/08 ,  H01L43/10 ,  H01L43/14 ,  H01L45/00

Abstract: Circuits are described that use metallization on both sides techniques to integrate two different types of non-volatile embedded memory devices within a single monolithic integrated circuit device. In an embodiment, a monolithic integrated circuit structure is provided that includes a device layer having one or more logic transistors. A front side interconnect layer is provided above the device layer, as seen in a vertical cross-section taken through the monolithic integrated circuit from top to bottom. A back side interconnect layer is provided below the device layer, as seen in the vertical cross-section. A first type of non-volatile memory device is provided in the front side interconnect layer, and a second type of non-volatile memory device different from the first type of non-volatile memory device is provided in the back side interconnect layer. A back side contact may be used to connect the device layer to a back side interconnect layer.

公开(公告)号：US20190326299A1

公开(公告)日：2019-10-24

申请号：US16474885

申请日：2017-04-04

Applicant: INTEL CORPORATION

Inventor： YIH WANG

IPC: H01L27/108

Abstract: An embedded dynamic random-access memory cell includes a wordline to supply a gate signal, a selector thin-film transistor (TFT) above the wordline and that includes an active layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the active layer in response to the gate signal, a bitline to transfer the memory state and coupled to and above the first region of the active layer, a storage node coupled to and above the second region of the active layer, and a metal-insulator-metal capacitor coupled to and above the storage node and configured to store the memory state. In an embodiment, the wordline is formed in a back end of line process for interconnecting logic devices formed in a front end of line process below the wordline, and the selector TFT is formed in a thin-film process.

公开(公告)号：US20190081233A1

公开(公告)日：2019-03-14

申请号：US16073687

申请日：2016-04-01

Applicant: INTEL CORPORATION

Inventor： KEVIN J. LEE ,  OLEG GOLONZKA ,  TAHIR GHANI ,  RUTH A. BRAIN ,  YIH WANG

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/14 ,  H01L43/08 ,  H01L43/10

Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.

公开(公告)号：US20220157820A1

公开(公告)日：2022-05-19

申请号：US17588938

申请日：2022-01-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20200152635A1

公开(公告)日：2020-05-14

申请号：US16473592

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  SHRIRAM SHIVARAMAN ,  YIH WANG ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/45

Abstract: Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20190198675A1

公开(公告)日：2019-06-27

申请号：US16329044

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： ABHISHEK A. SHARMA ,  VAN H. LE ,  GILBERT DEWEY ,  RAFAEL RIOS ,  JACK T. KAVALIEROS ,  YIH WANG ,  SHRIRAM SHIVARAMAN

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/50 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/50 ,  H01L29/66742 ,  H01L2224/16225 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure describe a non-planar gate thin film transistor. An integrated circuit may include a plurality of layers formed on a substrate, and the plurality of layers may include a first one of a source or drain, an inter-layer dielectric (ILD) formed on the first one of the source or drain, and a second one of the source or drain formed on the ILD. A semiconductive layer may be formed on a sidewall of the plurality of layers. A gate dielectric layer formed on the semiconductive layer, and a gate may be in contact with the gate dielectric layer.