公开(公告)号：US10236069B2

公开(公告)日：2019-03-19

申请号：US15627928

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C11/34

Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.

公开(公告)号：US09354973B2

公开(公告)日：2016-05-31

申请号：US13798370

申请日：2013-03-13

Applicant: Intel Corporation

Inventor： Yogesh B. Wakchaure ,  Xin Guo ,  Robert E. Frickey

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/108

Abstract: Data management logic allocates a portion such as a single plane of a respective multi-plane non-volatile memory device to store parity information for corresponding data striped across multiple planes of multiple non-volatile memory devices. According to one configuration, the data management logic as discussed herein generates parity data based on (a data stripe of) non-parity data stored in multiple planes of multiple different memory devices. The data management logic stores the parity data in the storage plane allocated to store the parity information. Additional configurations include: reserving a parity block amongst multiple non-parity data blocks to store parity data and reserving a parity page amongst multiple non-parity data pages to store parity data.

Abstract translation: 数据管理逻辑分配诸如相应的多平面非易失性存储器设备的单个平面的部分以存储用于在多个非易失性存储器设备的多个平面上条带化的相应数据的奇偶校验信息。 根据一种配置，本文所讨论的数据管理逻辑基于存储在多个不同存储器件的多个平面中的非奇偶校验数据（的数据条带）生成奇偶校验数据。 数据管理逻辑将奇偶校验数据存储在分配用于存储奇偶校验信息的存储平面中。 其他配置包括：在多个非奇偶校验数据块之间保留奇偶校验块以存储奇偶校验数据并且在多个非奇偶校验数据页之间保留奇偶校验页以存储奇偶校验数据。

公开(公告)号：US09817600B2

公开(公告)日：2017-11-14

申请号：US15377200

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

公开(公告)号：US09524774B2

公开(公告)日：2016-12-20

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56 ,  G11C16/34 ,  G06F12/02

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

公开(公告)号：US09679658B2

公开(公告)日：2017-06-13

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. Pelster ,  Yogesh B. Wakchaure ,  Xin Guo ,  Paul D. Ruby ,  Justin R. Dayacap ,  Joseph F. Doller ,  Robert E. Frickey

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

公开(公告)号：US20160054925A1

公开(公告)日：2016-02-25

申请号：US14877144

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。

公开(公告)号：US09543019B2

公开(公告)日：2017-01-10

申请号：US13710913

申请日：2012-12-11

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G06F11/10 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F11/1048 ,  G11C11/5628

Abstract: Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.

Abstract translation: 方法，设备和制造品可以接收第一页数据并且校正第一页数据中的一个或多个错误以产生校正数据的页面。 然后可以用第二页数据和校正数据的页面发送程序命令，以编程存储器页面以存储第二页数据。

公开(公告)号：US09183091B2

公开(公告)日：2015-11-10

申请号：US13628356

申请日：2012-09-27

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F9/445 ,  G06F11/14

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。

公开(公告)号：US09552159B2

公开(公告)日：2017-01-24

申请号：US14877144

申请日：2015-10-07

Applicant: Intel Corporation

Inventor： Ning Wu ,  Robert E. Frickey ,  Hanmant P. Belgal ,  Xin Guo

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/14

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0688 ,  G06F11/1417

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract translation: 根据一种配置，存储器系统包括配置管理器和多个存储器设备。 配置管理器包括状态检测逻辑，检索逻辑和配置管理逻辑。 状态检测逻辑接收由第一存储器设备进行的失败尝试的通知，以便通过存储在第一存储器设备中的自定义配置设置进行初始化。 响应于该通知，检索逻辑从存储器系统中的第二存储器设备检索配置设置信息的备份副本。 配置管理逻辑使用从第二存储器设备检索的配置设置信息的备份副本来初始化第一存储器设备。

公开(公告)号：US20160155497A1

公开(公告)日：2016-06-02

申请号：US14954002

申请日：2015-11-30

Applicant: Intel Corporation

Inventor： Robert E. Frickey ,  Yogesh B. Wakchaure ,  Iwen Chao ,  Xin Guo ,  Kristopher H. Gaewsky

IPC: G11C11/56

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C11/5628 ,  G11C16/3404 ,  G11C16/3418 ,  G11C2211/5641 ,  G11C2211/5646

Abstract: An electronic memory or controller may use a first type of read command, addressed to a first page of memory of an electronic memory that includes information to indicate that a second page of memory of the electronic memory has not been programmed and a second type of read command, addressed to the first page of memory, that includes information to indicate that the second page of memory has been programmed. The first page of memory may include a lower page of a multi-level cell (MLC), and the second page of memory may include an upper page of the same MLC. The second page of memory is enabled during a period of time that the first type of read command is used.

Abstract translation: 电子存储器或控制器可以使用第一类型的读取命令，寻址到电子存储器的存储器的第一页，其包括用于指示电子存储器的第二页存储器尚未被编程的信息和第二类型的读取 命令，寻址到存储器的第一页，其包括用于指示第二页存储器已被编程的信息。 存储器的第一页可以包括多级单元（MLC）的下页，并且第二页存储器可以包括相同MLC的上页。 在使用第一种类型的读取命令的时间段内启用第二页内存。