公开(公告)号：US20200220457A1

公开(公告)日：2020-07-09

申请号：US16820555

申请日：2020-03-16

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02M3/07 ,  H02M3/158 ,  H02J7/34

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

公开(公告)号：US10530254B2

公开(公告)日：2020-01-07

申请号：US15632086

申请日：2017-06-23

Applicant: INTEL CORPORATION

Inventor： Khondker Ahmed ,  Vivek De ,  Nachiket Desai ,  Suhwan Kim ,  Harish Krishnamurthy ,  Xiaosen Liu ,  Turbo Majumder ,  Krishnan Ravichandran ,  Christopher Schaef ,  Vaibhav Vaidya ,  Sriram Vangal

IPC: H02M3/158 ,  H02M1/08 ,  H02M1/00

Abstract: Embodiments described herein concern operating a peak-delivered-power (PDP) controller. Operating a PDP includes calculating the new power output value from the output voltage value and the output current value, determining whether the new power output value is greater than the previous power output value to determine whether the voltage regulator is outputting a maximum power output, based on a determination that the new power output value is greater than the previous power output value, providing an instruction to a duty generator to increase a duty cycle of the voltage regulator, based on a determination that the new power output value is not greater than the previous power output value, providing an instruction to the duty generator to decrease the duty cycle of the voltage regulator, and replacing the previous power output value with the new power output value.

公开(公告)号：US10379592B2

公开(公告)日：2019-08-13

申请号：US15462257

申请日：2017-03-17

Applicant: INTEL CORPORATION

Inventor： Dileep Kurian ,  Tanay Karnik ,  David Arditti Ilitzky ,  Ankit Gupta ,  Sriram Kabisthalam Muthukumar ,  Vaibhav Vaidya ,  Suhwan Kim ,  Christopher Schaef ,  Ilya Klochkov

IPC: G06F9/00 ,  G06F1/3212 ,  G06F1/3287 ,  G06F1/329

Abstract: The present disclosure provides for the management of power of a NZE IoT device. Managing power can include receiving the one or more asynchronous events from the asynchronous event system, determining if any of the one or more asynchronous events meet a respective charge qualification, generating the power-on command for the power-managed compute system if any of the one or more asynchronous events meet the respective charge qualification, and waiting for a power source to reach a threshold associated with the respective charge qualification if any of the one or more asynchronous events do not meet the respective charge qualification.

公开(公告)号：US09997942B2

公开(公告)日：2018-06-12

申请号：US14580825

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Lilly Huang ,  Suvankar Biswas ,  Vaibhav Vaidya ,  Krishnan Ravichandran

IPC: H02J7/00

CPC classification number: H02J7/007 ,  H01M10/44 ,  H01M10/465 ,  H02J7/0077 ,  H02J7/022 ,  H02J7/04

Abstract: In embodiments, apparatuses, methods and systems associated with battery charging are disclosed herein. In various embodiments, a reference current selector may receive a battery voltage sense input and output a reference current level signal, a power point check detector may receive a power supply sense input and output a power point check signal, and a controller coupled to the reference current selector and the power point check detector may receive a battery current sense input and switch a control output based at least in part on the reference current level signal, the battery current sense input, and the power point check signal. Other embodiments may be described and/or claimed.

公开(公告)号：US20170271873A1

公开(公告)日：2017-09-21

申请号：US15076444

申请日：2016-03-21

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Christopher Schaef ,  Vaibhav Vaidya ,  Suhwan Kim

IPC: H02J3/38 ,  H02M3/07

CPC classification number: H02M3/07 ,  H02J7/34 ,  H02M3/1582 ,  H02M2001/007

Abstract: Apparatuses, methods and storage medium associated with deriving power output from an energy harvester are disclosed herein. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to identify a plurality of times at which an intermediate voltage of a two stage power conversion circuit corresponds to a voltage reference, and ascertain an amount of time between one of the identified times and another one of the identified times. The one or more processors, devices, and/or circuitry may derive a power or current value associated with the second power supply using the amount of time.

公开(公告)号：US10938327B2

公开(公告)日：2021-03-02

申请号：US15721548

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Suhwan Kim ,  Vaibhav Vaidya ,  Christopher Schaef

IPC: H02N2/18 ,  H02N2/14 ,  H02M3/04 ,  H02M3/07

Abstract: An embodiment of a harvester apparatus comprising two or more charge pump stages may include at least a first charge pump stage to receive an alternating current source, and a second charge pump stage coupled to the first charge pump stage.

公开(公告)号：US10320197B2

公开(公告)日：2019-06-11

申请号：US14926975

申请日：2015-10-29

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Lilly Huang ,  Christopher Schaef

IPC: H01H47/00 ,  H02J4/00 ,  H02J7/00 ,  H02J7/34 ,  H02J7/35

Abstract: In an embodiment, a system includes controller circuitry to initiate a plurality of energy transfer cycles. Each energy transfer cycle includes an input time period during which corresponding input energy is received by a power train, and an output time period during which corresponding output energy is output from the power train. The system also includes energy detection logic to provide, upon completion of each energy transfer cycle, a corresponding indication of corresponding residual energy retained by the power train. Other embodiments are described and claimed.

公开(公告)号：US20180267591A1

公开(公告)日：2018-09-20

申请号：US15462257

申请日：2017-03-17

Applicant: INTEL CORPORATION

Inventor： Dileep Kurian ,  Tanay Karnik ,  David Arditti Ilitzky ,  Ankit Gupta ,  Sriram Kabisthalam Muthukumar ,  Vaibhav Vaidya ,  Suhwan Kim ,  Christopher Schaef ,  Ilya Klochkov

IPC: G06F1/32

CPC classification number: G06F1/3212 ,  G06F1/3287 ,  G06F1/329 ,  Y02D70/00 ,  Y02D70/26

Abstract: The present disclosure provides for the management of power of a NZE IoT device. Managing power can include receiving the one or more asynchronous events from the asynchronous event system, determining if any of the one or more asynchronous events meet a respective charge qualification, generating the power-on command for the power-managed compute system if any of the one or more asynchronous events meet the respective charge qualification, and waiting for a power source to reach a threshold associated with the respective charge qualification if any of the one or more asynchronous events do not meet the respective charge qualification.

公开(公告)号：US10069397B2

公开(公告)日：2018-09-04

申请号：US14757802

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Vaibhav Vaidya ,  Pavan Kumar ,  Krishnan Ravichandran ,  Vivek K. De

IPC: H02M1/08 ,  H02M1/38 ,  H02M3/158

Abstract: Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, IL,max. The difference between Vin and Vsw represents the maximum inductor current.

公开(公告)号：US09812952B2

公开(公告)日：2017-11-07

申请号：US14316334

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： Lilly Huang ,  Yang-Lin Chen ,  Vaibhav Vaidya

IPC: H02M3/04 ,  H02J1/14 ,  H02M3/156 ,  H02J7/34 ,  H02M1/00

CPC classification number: H02M3/04 ,  H02J7/34 ,  H02M3/156 ,  H02M2001/0048 ,  Y02B40/90 ,  Y02B70/1491

Abstract: Systems and methods may provide for a transient response apparatus that includes a single stage conversion module having a power input, a power output, and a control input, and a compensation module including a feedback input. The compensation module may be coupled to the power input, the power output and the control input of the single stage conversion module. Additionally, a feedback module may be coupled to the power output of the single stage conversion module and the feedback input of the compensation module. In one example, the feedback module includes a loop controller having a plurality of programmable inputs and an error output, and a modulus unit coupled to the error output of the loop controller and the feedback input of the compensation module.