公开(公告)号：US20240242740A1

公开(公告)日：2024-07-18

申请号：US18622813

申请日：2024-03-29

Applicant: Intel Corporation

Inventor： Phil GENG ,  Xiang LI ,  George VERGIS

IPC: G11C5/04 ,  H05K1/14 ,  H05K1/18

CPC classification number: G11C5/04 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189

Abstract: A retainer to inhibit movement of dual in-line memory modules (DIMMs) that are removably inserted into connectors attached to a printed circuit board (PCB) of a system. Inhibiting movement of the DIMMs, especially taller DIMMs, such as the higher height 2 U and 4 U DIMMs, mitigates the effects of operational vibration causing intermittent electrical discontinuity between DIMM and the PCB. The retainer inhibits movement of DIMMs at the connector component level by constraining all or a portion of top edges of DIMMs inserted into connectors. The retainer is implemented independently of the design of the system-level chassis. The retainer is shaped into any of a bracket or frame from multiple rigid horizontal, vertical and oblique members that permit airflow to the DIMMs and connectors retained therein.

公开(公告)号：US20230137619A1

公开(公告)日：2023-05-04

申请号：US18088460

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Xiang LI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  G06F1/18

Abstract: A circuit board includes vias with a coil structure. A circuit board includes vias with barrels that extend vertically through the circuit board and pads in different planes of the circuit board, such as the top surface and bottom surface, and optionally in an inner routing layer. The coil structure is a coil of conductor in a plane of the circuit board, electrically connected to a pad in that plane, which is electrically connected to the barrel. The coil structure provides self-inductance around the pad, which brings up the reactive impedance of the via to balance the capacitive reactance of the via.

公开(公告)号：US20230044892A1

公开(公告)日：2023-02-09

申请号：US17969518

申请日：2022-10-19

Applicant: Intel Corporation

Inventor： Xiang LI ,  Saravanan SETHURAMAN ,  George VERGIS ,  James A. McCALL

IPC: H05K1/11 ,  H01L25/18 ,  H05K1/18

Abstract: According to examples, a memory module with module rows of conductive contacts can enable multiple memory channels to be connected to the same memory module. In one example, a memory module includes a printed circuit board (PCB) having a first face, a second face, and an edge to be received by a connector. The memory module includes a plurality of memory chips on at least one of the first and second faces of the PCB. The memory module includes two or more rows of conductive contacts on each of the first and second faces of the PCB, the two rows including a first row of conductive contacts proximate to the edge of the PCB to be received by the connector, and a second row of conductive contacts between the first row and a second edge of the PCB opposite to the first edge.

公开(公告)号：US20220368047A1

公开(公告)日：2022-11-17

申请号：US17874111

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： George VERGIS ,  Xiang LI ,  Jun LIAO ,  Anthony M. CONSTANTINE ,  Min Suet LIM ,  Tongyan ZHAI ,  Konika GANGULY

IPC: H01R12/72 ,  G06F1/18 ,  H01R13/24 ,  H01R12/70

Abstract: An adapter card with compression-attached memory modules that can be inserted into a conventional vertical connector enables use of CAMMs in systems with vertical memory module connectors. In one example, an adapter card or riser card includes a printed circuit board (PCB) having an edge to be received by a dual-inline memory module (DIMM) connector. First conductive contacts proximate to the edge of the PCB are to be received by the DIMM connector, enabling the first conductive contacts to couple with contacts of the DIMM connector. Second conductive contacts on a face of the PCB are to couple with a first compression attached memory module (CAMM) via a first compression mount technology (CMT) connector. The adapter card includes conductive traces on or in the PCB between the first conductive contacts and the second conductive contacts to couple the CAMM with the DIMM connector.

公开(公告)号：US20220263262A1

公开(公告)日：2022-08-18

申请号：US17737243

申请日：2022-05-05

Applicant: Intel Corporation

Inventor： Landon HANKS ,  Xiang LI ,  George VERGIS ,  James A. McCALL

IPC: H01R13/24 ,  H01R13/652 ,  H01R13/04 ,  H01R12/71

Abstract: Examples described herein relate to a system that includes: a first signal pin and a first ground pin adjacent to the first signal pin. In some examples, the first signal pin comprises a first portion, a second portion, and a third portion. In some examples, the first ground pin comprises a first portion, a second portion, and a third portion, the second portion of the first signal pin comprises a vertical mount, the second portion of the first ground pin comprises a vertical mount, and the second portion of the first signal pin and the second portion of the first ground pin are arranged proximate one another.

公开(公告)号：US20210153351A1

公开(公告)日：2021-05-20

申请号：US17127829

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Xiang LI ,  George VERGIS ,  Jeffrey KRIEGER

IPC: H05K1/11 ,  H01R12/52 ,  H05K5/02 ,  H05K1/18 ,  G11C5/06

Abstract: Connectors with a hybrid pitch are described. In one example, a connector to couple a card or module to a motherboard includes connector housing and a plurality of pins. The plurality of pins include alternating signal and ground pins. Each of the plurality of pins includes a card or module-facing end to couple with the card or module and a lead to couple with a through hole in the motherboard. A first pitch between leads of a pin and a first adjacent pin is different than a second pitch between leads of the pin and a second adjacent pin.

公开(公告)号：US20210120670A1

公开(公告)日：2021-04-22

申请号：US17134028

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Guixiang TAN ,  Xiang LI ,  Casey WINKEL ,  George VERGIS

IPC: H05K1/11 ,  H05K5/02 ,  H05K5/00 ,  H05K7/20

Abstract: An apparatus is described. The apparatus includes a printed circuit board (PCB) dual in-line memory module (DIMM) connector having ejectors. The ejectors have a small enough vertical profile to permit unbent liquid cooling conduits to run across the DIMM's semiconductor chips.

公开(公告)号：US20190045622A1

公开(公告)日：2019-02-07

申请号：US15817098

申请日：2017-11-17

Applicant: Intel Corporation

Inventor： Jun LIAO ,  Zhen ZHOU ,  James A. McCALL ,  Jong-Ru GUO ,  Xiang LI ,  Yunhui CHU ,  Zuoguo WU

IPC: H05K1/02 ,  H05K1/14

Abstract: An apparatus is described. The apparatus includes a semiconductor chip having cross-talk noise cancellation circuitry disposed between a disturber trace and a trace to be protected from cross-talk noise emanating from the disturber trace. The trace is to be coupled to a receiver disposed on a different semiconductor chip.

公开(公告)号：US20180189214A1

公开(公告)日：2018-07-05

申请号：US15396268

申请日：2016-12-30

Applicant: INTEL CORPORATION

Inventor： James A. MCCALL ,  Zhichao ZHANG ,  Qin LI ,  Xiang LI ,  John R. DREW

IPC: G06F13/40 ,  H01R12/72

CPC classification number: G06F13/4022 ,  G06F13/4068 ,  H01R12/721

Abstract: Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways. Other embodiments are described and claimed.

公开(公告)号：US20230070411A1

公开(公告)日：2023-03-09

申请号：US17987382

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Min LIU ,  Xiang LI ,  Shijie LIU ,  Yannan SUN ,  Lei ZHU

IPC: G06F3/06 ,  G06F12/0815

Abstract: Examples described herein relate to a central processing unit (CPU) that includes at least two cores, at least two caching agents (CAs), and circuitry to monitor a workload mapped to a CA of the at least two CAs and adjust the workload allocated to the CA to allocation among the CA and at least one other CA of the at least two CAs based on the monitored workload.