公开(公告)号：US20180287305A1

公开(公告)日：2018-10-04

申请号：US15476582

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Youngseok Oh ,  Justin M. Huttula ,  Mohanraj Probhugoud ,  Ronald Kirby ,  Joe Walczyk ,  Erkan Acar

IPC: H01R13/6594 ,  H01R13/11 ,  H01R13/6585 ,  H01R13/66 ,  H01R43/26

Abstract: A shielded interconnect array and associated methods are described. Examples of the shielded interconnect array include socket connections that include conductive members with flexible bends. In examples shown, corresponding grounded conductive members with flexible bends are located adjacent to other conductive members with flexible bends to provide shielding.

公开(公告)号：US09674943B2

公开(公告)日：2017-06-06

申请号：US13707032

申请日：2012-12-06

Applicant: Intel Corporation

Inventor： Youngseok Oh ,  Joe Walczyk

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K1/0268 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/4046

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US09523713B2

公开(公告)日：2016-12-20

申请号：US13903874

申请日：2013-05-28

Applicant: INTEL CORPORATION

Inventor： Youngseok Oh ,  Joe F. Walczyk ,  Jin Yang ,  Pooya Tadayon ,  Ting Zhong

IPC: G01R1/067 ,  G01R1/073

CPC classification number: G01R1/06783 ,  G01R1/07307 ,  Y10T29/49124

Abstract: Embodiments of the present disclosure are directed to interconnects that include liquid metal, and associated techniques and configurations. The individual interconnects may electrically couple a contact of a printed circuit board (PCB) to a contact of a device under test (DUT). The interconnect may be disposed in or on the PCB. In various embodiments, the interconnect may include a carrier that defines a well (e.g., an opening in the carrier), and the liquid metal may be disposed in the well. In some embodiments, the contact of the DUT, or a contact of an intermediary device, may extend into the well and directly contact the liquid metal. In other embodiments, a flex circuit may be disposed over the well to seal the well. The flex circuit may include a conductive pad to electrically couple the liquid metal to the contact of the DUT. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例涉及包括液态金属以及相关技术和配置的互连。 各个互连可以将印刷电路板（PCB）的触点电耦合到被测器件（DUT）的触点。 互连可以设置在PCB中或PCB上。 在各种实施例中，互连可以包括限定阱（例如，载体中的开口）的载体，并且液体金属可以设置在阱中。 在一些实施例中，DUT或中间装置的触点的接触可以延伸到井中并直接接触液态金属。 在其他实施例中，柔性电路可以设置在井上以密封井。 柔性电路可以包括用于将液体金属电耦合到DUT的触点的导电焊盘。 可以描述和要求保护其他实施例。

公开(公告)号：US11656247B2

公开(公告)日：2023-05-23

申请号：US16473378

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ronald Michael Kirby ,  Erkan Acar ,  Joe Walczyk ,  Youngseok Oh ,  Justin M Huttula ,  Mohanraj Prabhugoud

IPC: G01R1/07 ,  G01R1/04 ,  G01R1/073

CPC classification number: G01R1/07357 ,  G01R1/0466

Abstract: A coaxial wire interconnect architecture and associated methods are described. In one example, the coaxial wire interconnect architecture is used in a test socket interconnect array. Flexible bends are formed in one or more of the coaxial wire interconnects to provide compliant connections to an electronic device during testing.

公开(公告)号：US20170273176A1

公开(公告)日：2017-09-21

申请号：US15614182

申请日：2017-06-05

Applicant: Intel Corporation

Inventor： Youngseok Oh ,  Joe Walczyk

IPC: H05K1/02

CPC classification number: H05K1/0268 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/116 ,  H05K3/4046

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. In one such embodiment, an apparatus may include an electronic arrangement, a first die, and a second die coupled to the first die and the electronic arrangement. The electronic arrangement may include an opening. At least a portion of the die may occupy at least a portion of the opening in the electronic arrangement. Other embodiments including additional apparatuses and methods are described.

公开(公告)号：US20160178663A1

公开(公告)日：2016-06-23

申请号：US14581508

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Mohanraj Prabhugoud ,  Youngseok Oh ,  Joseph F. Walczyk ,  Todd P. Albertson

IPC: G01R1/04 ,  G01R1/073 ,  G01R1/067

CPC classification number: G01R1/07357 ,  G01R1/0466 ,  G01R1/0483

Abstract: A test die contactor is described with a formed wire probe interconnect. In one example the contactor includes a plurality of wire probes formed to be resilient against longitudinal pressure, a first aligner proximate one end of the wire probes having a first plurality of holes through which the wire probes extend, the first alignment layer to align the wire probes to contact pads of a text fixture, a second aligner proximate the other end of the wire probes having a second plurality of holes through the wire probes extend, the second alignment layer to align the wire probes to contact pads of a device under test, and an insulating layer between the first and the second aligner through which the wire probes extend to hold the wire probes when compressed by longitudinal pressure.

Abstract translation: 使用形成的导线探针互连来描述测试模具接触器。 在一个示例中，接触器包括形成为抵抗纵向压力弹性的多个线探针，靠近线探头的一端的第一对准器具有第一多个孔，线探针延伸穿过该第一多个孔，第一对准层对准线 探针到文本夹具的接触垫，靠近导线探针的另一端的第二对准器具有穿过线探头的第二多个孔延伸，第二对准层将线探针对准待测器件的接触垫， 以及在第一和第二对准器之间的绝缘层，当通过纵向压力压缩时，线探针延伸通过该绝缘层保持线探头。