公开(公告)号：US09523713B2

公开(公告)日：2016-12-20

申请号：US13903874

申请日：2013-05-28

Applicant: INTEL CORPORATION

Inventor： Youngseok Oh ,  Joe F. Walczyk ,  Jin Yang ,  Pooya Tadayon ,  Ting Zhong

IPC: G01R1/067 ,  G01R1/073

CPC classification number: G01R1/06783 ,  G01R1/07307 ,  Y10T29/49124

Abstract: Embodiments of the present disclosure are directed to interconnects that include liquid metal, and associated techniques and configurations. The individual interconnects may electrically couple a contact of a printed circuit board (PCB) to a contact of a device under test (DUT). The interconnect may be disposed in or on the PCB. In various embodiments, the interconnect may include a carrier that defines a well (e.g., an opening in the carrier), and the liquid metal may be disposed in the well. In some embodiments, the contact of the DUT, or a contact of an intermediary device, may extend into the well and directly contact the liquid metal. In other embodiments, a flex circuit may be disposed over the well to seal the well. The flex circuit may include a conductive pad to electrically couple the liquid metal to the contact of the DUT. Other embodiments may be described and claimed.

Abstract translation: 本公开的实施例涉及包括液态金属以及相关技术和配置的互连。 各个互连可以将印刷电路板（PCB）的触点电耦合到被测器件（DUT）的触点。 互连可以设置在PCB中或PCB上。 在各种实施例中，互连可以包括限定阱（例如，载体中的开口）的载体，并且液体金属可以设置在阱中。 在一些实施例中，DUT或中间装置的触点的接触可以延伸到井中并直接接触液态金属。 在其他实施例中，柔性电路可以设置在井上以密封井。 柔性电路可以包括用于将液体金属电耦合到DUT的触点的导电焊盘。 可以描述和要求保护其他实施例。

公开(公告)号：US20180045759A1

公开(公告)日：2018-02-15

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R31/28

CPC classification number: G01R1/07328 ,  G01B7/003 ,  G01R1/06794 ,  G01R31/2891

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US11935860B2

公开(公告)日：2024-03-19

申请号：US16828651

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Morten Jensen ,  Michael Ryan ,  Srikant Nekkanty ,  Joe F. Walczyk

IPC: H01L23/00 ,  H01R12/71 ,  H01R13/24

CPC classification number: H01L24/32 ,  H01L24/67 ,  H01R12/714 ,  H01R13/2421 ,  H01R13/2485 ,  H01R13/2492

Abstract: An interconnect that has an electrically conductive layer, where a first and second insulator layers are coupled with the conductive layer. A region of the conductive layer includes an opening of a portion of the first insulator layer the second insulator layer that are adjacent to the region. An electrical connector of a first device is electrically coupled to a portion of the region on a first side of the conductive layer and an electrical conductor of a second device is electrically coupled with a portion of the region on the second side. Also, an interconnect coupled with a substrate that includes a cylinder extending from a side of the substrate with a plate coupled at the end of the cylinder with an opening that includes two or more tabs of the plate extending into the opening to receive a connector.

公开(公告)号：US11581237B2

公开(公告)日：2023-02-14

申请号：US16012126

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Joe F. Walczyk ,  Pooya Tadayon

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/46 ,  H01L23/373

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

公开(公告)号：US20200371155A1

公开(公告)日：2020-11-26

申请号：US16417408

申请日：2019-05-20

Applicant: INTEL CORPORATION

Inventor： Joe F. Walczyk ,  James Hastings ,  Morten Jensen ,  Todd Coons

IPC: G01R31/28

Abstract: An apparatus for testing integrated circuits (ICs), comprising a first thermal contact structure having a first surface to interface with a heat source, the first surface is opposite a second surface. A second thermal contact structure is above the first thermal contact structure and separated therefrom. The second thermal contact structure has a third surface to interface with a cold mass. The third surface is opposite a fourth surface, and the fourth surface is opposite the second surface. A variable-resistance thermal interface (VRTI) structure is between the first and second thermal contact structures. The VRTI structure has a maximal thermal conductivity associated with a first state, and a minimal thermal conductivity associated with a second state.

公开(公告)号：US20200072871A1

公开(公告)日：2020-03-05

申请号：US16490517

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Joe F. Walczyk ,  Keith J. Marting

IPC: G01R1/073 ,  H05K1/11 ,  H05K3/42 ,  H05K3/00 ,  H05K3/40

Abstract: Space transformation technology for probe cards at sort is disclosed. In one example, a space transformer transforms a pitch of electrical contacts from a first distribution to a second distribution. The space transformer comprises a substrate with opposite first and second sides; and vias extending through the substrate between the first and second sides and oriented at different angles with respect to one another. In one example, a tester system or probe card for a die comprises a printed circuit board (PCB) with pads having a pad pitch; and a space transformer operatively coupled to the PCB, and having vias extending from the pads of the PCB through the space transformer at different angles with respect to one another and configured to electrically connect to contacts on the die having a contact pitch different than the pad pitch.

公开(公告)号：US12061230B2

公开(公告)日：2024-08-13

申请号：US17131604

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G01R31/308 ,  G02B6/42

CPC classification number: G01R31/308 ,  G02B6/4256 ,  G02B6/4292

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to active optical plugs used to cover optical connectors of a photonics package to protect the connectors. The active optical plugs may also be used to perform testing of the photonics package, including generating light to be sent to the photonics package and to detect light received from the photonics package as part of the test protocol. This allows testing the optical connection and the photonics package, without exposing the optical connections of the package to damage from dust or physical contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20190385925A1

公开(公告)日：2019-12-19

申请号：US16012126

申请日：2018-06-19

Applicant: Intel Corporation

Inventor： Joe F. Walczyk ,  Pooya Tadayon

IPC: H01L23/367 ,  H01L21/48 ,  H01L23/46

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

公开(公告)号：US10324112B2

公开(公告)日：2019-06-18

申请号：US15370870

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  Andrew J. Hoitink ,  Abram M. Detofsky ,  Joe F. Walczyk

IPC: G01R1/073 ,  G01B7/00 ,  G01R1/067 ,  G01R31/28

Abstract: Embodiments of the present disclosure provide techniques and configurations for a package testing system. In some embodiments, the system may comprise a printed circuit board (PCB), including one or more sensors disposed adjacent to a corner of the PCB to face a package to be tested, to detect an electrical edge of the package. The PCB may include a contactor array disposed to face respective interconnects of the package. The system may further include a controller coupled with the one or more sensors, to process an input from the one or more sensors, to identify the electrical edge of the package, and initiate an adjustment of a position of the PCB relative to the package, based at least in part on the electrical edge of the package, to substantially align contacts of the contactor array with the respective interconnects of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US12135460B2

公开(公告)日：2024-11-05

申请号：US17132912

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Todd R. Coons ,  Michael Rutigliano ,  Joe F. Walczyk ,  Abram M. Detofsky

IPC: G02B6/42 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34 ,  H01L25/075 ,  H01L33/58 ,  H01L33/62 ,  H01L23/367 ,  H04B10/40

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to incorporating photonics integrated circuitry into a base die, the base die including an optical interconnect at a bottom of the base die to transmit and to receive light signals from outside the base die. The top of the base die includes one or more electrical connectors that are electrically coupled with the photonics integrated circuitry. The base die may be referred to as the photonics die. A system-on-a-chip (SOC) may be electrically coupled with and stacked onto the top of the photonics die. Other embodiments may be described and/or claimed.