公开(公告)号：US12266393B2

公开(公告)日：2025-04-01

申请号：US18065195

申请日：2022-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Nicholas Anthony Lanzillo

IPC: G11C11/22 ,  H10B53/30 ,  H10D1/68

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

公开(公告)号：US20250048675A1

公开(公告)日：2025-02-06

申请号：US18365990

申请日：2023-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Reinaldo Vega ,  Takashi Ando ,  James P. Mazza ,  Nicholas Anthony Lanzillo ,  David Wolpert

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate and a transistor positioned on the substrate. The transistor includes transistor includes a channel region, a shared gate region, and a source and drain region. The source and drain region includes a concave outer wall includes a concave outer wall. A method of manufacturing a semiconductor device includes providing a substrate and forming a plurality of transistor gate structures on the substrate. A source and drain region are formed and positioned adjacent the plurality of transistor gate structures. A concave wall is recessed into material of the source and drain region toward a centerline of the source and drain region.

公开(公告)号：US20240220696A1

公开(公告)日：2024-07-04

申请号：US18092126

申请日：2022-12-30

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Biswanath Senapati ,  Lawrence A. Clevenger

IPC: G06F30/392 ,  G06F30/33 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/33 ,  G06F30/394 ,  G06F2119/18

Abstract: A semiconductor structure includes a first backside metal rail that extends across the structure and a second backside metal rail parallel and adjacent to the first backside metal rail. The first and second backside metal rails bound a first circuit row. The structure also includes a backside signal wire that interrupts the second backside metal rail; and a third backside metal rail that extends across the structure parallel and adjacent to the second backside metal rail. The second and third backside metal rails bound a second circuit row. The structure also includes gate metal pitches, which extend across the structure perpendicular to the backside metal rails. The structure also includes a frontside signal wire above the gate metal pitches; and a signal via that penetrates the structure and connects the backside signal wire to the frontside signal wire.

公开(公告)号：US11916099B2

公开(公告)日：2024-02-27

申请号：US17341489

申请日：2021-06-08

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L29/51 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L29/516

Abstract: A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.

公开(公告)号：US11906570B2

公开(公告)日：2024-02-20

申请号：US18296519

申请日：2023-04-06

Applicant: International Business Machines Corporation

Inventor： Christopher Gonzalez ,  David Wolpert ,  Michael Hemsley Wood

IPC: G01R31/26 ,  G01R31/28 ,  G06F30/3312 ,  G06F117/12 ,  G06F119/12

CPC classification number: G01R31/2623 ,  G01R31/2884 ,  G06F30/3312 ,  G06F2117/12 ,  G06F2119/12

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

公开(公告)号：US20230090855A1

公开(公告)日：2023-03-23

申请号：US17479246

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Basanth Jagannathan ,  Michael Hemsley Wood ,  Leon Sigal ,  James Leland ,  Alexander Joel Suess ,  Benjamin Neil Trombley ,  Paul G. Villarrubia

IPC: H02J3/00

Abstract: Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.

公开(公告)号：US20230086010A1

公开(公告)日：2023-03-23

申请号：US17480551

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Christopher Gonzalez ,  David Wolpert ,  Michael Hemsley Wood

IPC: G01R31/26 ,  G01R31/28 ,  G06F30/3312

Abstract: A method is provided to increase processor frequency in an integrated circuit (IC). The method includes identifying a gate included in the IC, the gate having a gate threshold voltage and performing a plasma process to form an antenna signal path in signal communication with the gate. The method further comprises adjusting the plasma process or circuit design to increase plasma induced damage (PID) applied to the gate so as to alter the gate threshold voltage.

公开(公告)号：US20230050432A1

公开(公告)日：2023-02-16

申请号：US17399397

申请日：2021-08-11

Applicant: International Business Machines Corporation

Inventor： David Wolpert ,  Leon Sigal ,  Michael Stewart Gray ,  Mitchell R. DeHond

IPC: G06F30/392 ,  G06F30/398 ,  G03F1/70

Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

公开(公告)号：US11055465B2

公开(公告)日：2021-07-06

申请号：US16559967

申请日：2019-09-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： David Wolpert ,  Timothy A. Schell ,  Michael Gray ,  Erwin Behnen ,  Robert Mahlon Averill, III

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/398 ,  G06F30/39 ,  G06F111/20 ,  G06F115/08 ,  G06F119/22 ,  G06F119/02 ,  G06F119/18 ,  G06F117/12

Abstract: Methods, systems and computer program products for avoiding Boolean DRC failures during cell placement are provided. Aspects include generating a semiconductor layout by filling a plurality of rows within a macro block with cells including functional cells and fill cells. Aspects also include modifying the semiconductor layout by removing one or more fill cells from the macro block to create a gap. Aspects also include examining a set of cells that border edges of the gap to identify one or more predicted rule violations. Based on the identified one or more predicted rule violations, aspects also include modifying the semiconductor layout to change a shape of the gap to avoid the one or more predicted rule violations.

公开(公告)号：US10896283B1

公开(公告)日：2021-01-19

申请号：US16543070

申请日：2019-08-16

Applicant: International Business Machines Corporation

Inventor： Kyle Indukummar Giesen ,  Samuel Sagan ,  David Wolpert

IPC: G06F17/50 ,  G06F30/398 ,  G06F30/20 ,  G06F30/394 ,  G06F30/3308

Abstract: An example operation may include one or more of generating a noise map which comprises one or more noise shapes for one or more electrical components on a substrate of a circuit, modifying a design of the one or more electrical components in a pre-production design of the circuit based on the noise map and one or more noise rules of the circuit, and outputting an updated design of the circuit which includes the modified design of the one or more electrical components.