公开(公告)号：US20190386135A1

公开(公告)日：2019-12-19

申请号：US16007263

申请日：2018-06-13

Applicant: International Business Machines Corporation

Inventor： Juntao LI ,  Kangguo CHENG ,  Choonghyun LEE ,  Peng XU

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L21/768 ,  H01L29/45 ,  H01L29/08

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and at least one semiconductor fin contacting the substrate. A first source/drain layer contacts the substrate. A silicide contacts and wraps around the first source/drain layer. The structure also includes a second source/drain layer above the first source/drain layer. The method comprises forming a structure including at least a substrate, a first source/drain layer, and at least one semiconductor fin disposed on and in contact with substrate. A silicide is formed in contact with and wrapping around the first source/drain layer. A gate structure is formed in contact with at least the at least one semiconductor fin. A second source/drain layer is formed above the first source/drain layer.

公开(公告)号：US20180096990A1

公开(公告)日：2018-04-05

申请号：US15591278

申请日：2017-05-10

Applicant: International Business Machines Corporation

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/764 ,  H01L21/823468 ,  H01L23/5283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4991 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

公开(公告)号：US20190296129A1

公开(公告)日：2019-09-26

申请号：US16424904

申请日：2019-05-29

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Peng XU

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L21/265 ,  H01L27/12

Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.

公开(公告)号：US20180308837A1

公开(公告)日：2018-10-25

申请号：US15991143

申请日：2018-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/7851

Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.

公开(公告)号：US20180097059A1

公开(公告)日：2018-04-05

申请号：US15285728

申请日：2016-10-05

Applicant: International Business Machines Corporation

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L29/06 ,  H01L21/764 ,  H01L29/40 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/764 ,  H01L21/823468 ,  H01L23/5283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4991 ,  H01L29/775 ,  H01L29/78

Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench.

公开(公告)号：US20180097000A1

公开(公告)日：2018-04-05

申请号：US15795753

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L27/088 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/265

CPC classification number: H01L27/0886 ,  H01L21/02233 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/0692 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

公开(公告)号：US20180096996A1

公开(公告)日：2018-04-05

申请号：US15285739

申请日：2016-10-05

Applicant: International Business Machines Corporation

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/02233 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823487 ,  H01L29/0692 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes a first source/drain disposed in contact with a substrate. A second source/drain is disposed above the first source/drain. At least one fin structure is disposed between and in contact with the first source/drain and the second source/drain. A width of the first source/drain and the second source/drain gradually decreases towards the fin structure. The method includes forming an oxide in contact with an exposed portion of at least one fin structure. During formation of the oxide, different areas of the exposed fin structure portion are oxidized at different rates. This forms a first region and a second region of the exposed fin structure portion. These regions each have a width that is greater than a width of a third region of the exposed fin structure portion situated between the first and second regions.

公开(公告)号：US20200295132A1

公开(公告)日：2020-09-17

申请号：US16351801

申请日：2019-03-13

Applicant: International Business Machines Corporation

Inventor： Chen ZHANG ,  Peng XU ,  Chun Wing YEUNG

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/786

Abstract: A semiconductor device and method for forming the same. The device comprises at least a dielectric layer, a two-dimensional (2D) material layer, a gate structure, and source/drain contacts. The 2D material layer contacts the dielectric layer. The gate structure contacts the 2D material layer. The source/drain contacts are disposed above the 2D material layer and contact the gate structure. The method includes forming a structure including at least a handle wafer, a 2D material layer, a gate structure in contact with the 2D material layer, an insulating layer, and a sacrificial layer. A portion of the sacrificial layer is etched. An inter-layer dielectric is formed in contact with the insulating layer and sidewalls of the sacrificial layer. The sacrificial layer and a portion of the insulating layer are removed. Source and drain contacts are formed in contact with the portion of the 2D material layer.

公开(公告)号：US20180122915A1

公开(公告)日：2018-05-03

申请号：US15856309

申请日：2017-12-28

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Peng XU ,  Chen ZHANG

IPC: H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L29/51 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/482 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/785

Abstract: A method (and structure) of fabricating an MOSFET (metal-oxide-semiconductor field-effect transistor), includes, on a gate structure coated with a high-k sidewall spacer film, etching off the high-k sidewall spacer film from a top surface of the gate structure and from a portion of vertical walls of the gate structure. The etched-off high-k sidewall spacer film on the vertical walls is replaced with an ultra low-k material.

公开(公告)号：US20180233560A1

公开(公告)日：2018-08-16

申请号：US15950231

申请日：2018-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo CHENG ,  Peng XU

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924

Abstract: A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain relaxation buffer layer, where the first portion of the strain relaxation buffer layer has a second width and a second semiconductor fin having a width substantially similar to the first width, the second semiconductor fin is arranged on a second portion of the strain relaxation buffer layer, where the second portion of the strain relaxation buffer layer has a third width. A gate stack is arranged over a channel region of the first fin and a channel region of the second fin.