公开(公告)号：US20200266288A1

公开(公告)日：2020-08-20

申请号：US16581867

申请日：2019-09-25

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Ruilong Xie ,  Chanro PARK

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: A semiconductor device structure and method for fabricating the same. The semiconductor device structure includes a semiconductor fin and a liner in contact with end portions of the semiconductor fin. A first source/drain contacts the liner and sidewalls of the semiconductor fin. A gate structure is in contact with and surrounds the semiconductor fin. A second source/drain is formed above the first source/drain. The method includes forming, on a substrate, at least one semiconductor fin having a first spacer in contact with an upper portion of the semiconductor fin, and a second spacer in contact with the first spacer and a lower portion of the semiconductor fin. The semiconductor fin is patterned into a plurality of semiconductor fins. A liner is formed on exposed end portions of each semiconductor fin of the plurality of semiconductor fins.

公开(公告)号：US20180069024A1

公开(公告)日：2018-03-08

申请号：US15795454

申请日：2017-10-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/76281 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66583 ,  H01L29/7838 ,  H01L29/7842 ,  H01L29/78684

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20180068948A1

公开(公告)日：2018-03-08

申请号：US15810531

申请日：2017-11-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Juntao LI

IPC: H01L23/525 ,  H01L21/8234 ,  H01H69/02 ,  H01C17/00

CPC classification number: H01L23/5256 ,  H01C17/006 ,  H01H69/022 ,  H01L21/31051 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5228 ,  H01L23/5329 ,  H01L23/535 ,  H01L27/0617 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

公开(公告)号：US20170323952A1

公开(公告)日：2017-11-09

申请号：US15356979

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Juntao LI ,  Xin Miao

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7853

Abstract: Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners provide a stress on the one or more channel structures. A gate is formed over and around the one or more channel structures, defining a channel region of the one or more channel structures that is covered by the gate. A source and drain region are formed on opposite sides of the gate.

公开(公告)号：US20200328211A1

公开(公告)日：2020-10-15

申请号：US16381129

申请日：2019-04-11

Applicant: International Business Machines Corporation

Inventor： Zhenxing BI ,  Kangguo Cheng ,  Juntao LI ,  Peng XU

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L21/8238

Abstract: An integrated semiconductor device having a substrate with a first substrate region and a second substrate region. The integrated semiconductor device further includes a first field-effect transistor disposed on the substrate in the first substrate region. The first filed-effect transistor has a plurality of first fins having a first semiconductor material. In addition, the integrated semiconductor device includes a second field-effect transistor disposed on the substrate in the second substrate region. The second field-effect transistor has a plurality of second fins having a second semiconductor material that differs from the first semiconductor material.

公开(公告)号：US20190189739A1

公开(公告)日：2019-06-20

申请号：US15844725

申请日：2017-12-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Juntao LI ,  Kangguo CHENG ,  Chen ZHANG ,  Xin MIAO

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/161

Abstract: A technique relates to a semiconductor device. A stack includes two or more nanowires separated by a high-k dielectric material, the high-k dielectric material being formed on at least a center portion of the two or more nanowires in the stack. A separation space between the two or more nanowires is less than two times a thickness of the high-k dielectric material formed on a side wall of the two or more nanowires. A source or a drain formed on sides of the stack.

公开(公告)号：US20190019811A1

公开(公告)日：2019-01-17

申请号：US16124291

申请日：2018-09-07

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Zuoguang LIU ,  Xin MIAO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/285 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02 ,  H01L21/84 ,  H01L29/66

Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

公开(公告)号：US20190006510A1

公开(公告)日：2019-01-03

申请号：US16112841

申请日：2018-08-27

Applicant: International Business Machines Corporation

Inventor： Kangguo CHENG ,  Juntao LI ,  Xin MIAO

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/161 ,  H01L29/08

CPC classification number: H01L29/785 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.

公开(公告)号：US20190019752A1

公开(公告)日：2019-01-17

申请号：US16132922

申请日：2018-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Veeraraghavan S. BASKER ,  Kangguo CHENG ,  Ali KHAKIFIROOZ ,  Juntao LI

IPC: H01L23/525 ,  H01L49/02 ,  H01L29/66 ,  H01L23/535 ,  H01L23/532 ,  H01L27/06 ,  H01H69/02 ,  H01C17/00 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/49 ,  H01L23/522

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

公开(公告)号：US20180308837A1

公开(公告)日：2018-10-25

申请号：US15991143

申请日：2018-05-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Zhenxing BI ,  Kangguo CHENG ,  Juntao LI ,  Peng XU

IPC: H01L27/06 ,  H01L29/78 ,  H01L49/02 ,  H01L21/3205 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/32055 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L28/20 ,  H01L29/0649 ,  H01L29/7851

Abstract: A technique relates to forming resistor fins on a substrate. A shallow trench isolation material is formed on dummy fins and the substrate, and the dummy fins are formed on the substrate. Predefined ones of the dummy fins are removed, thereby forming voids in the shallow trench isolation material corresponding to previous locations of the predefined ones of the dummy fins. A first material is deposited into the voids. The height of the first material is reduced, thereby forming trenches in the shallow trench isolation material. A second material is deposited into the trenches to be on top of the first material, thereby forming the resistor fins of a resistor device. A metal contact layer is formed so as to contact a top surface of the first material at predefined locations.