公开(公告)号：US20220157733A1

公开(公告)日：2022-05-19

申请号：US16950453

申请日：2020-11-17

Applicant: International Business Machines Corporation

Inventor： Ching-Tzu Chen ,  Nicholas Anthony Lanzillo ,  Vijay Narayanan ,  Takeshi Nogami

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

公开(公告)号：US11195929B2

公开(公告)日：2021-12-07

申请号：US16668473

申请日：2019-10-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  ULVAC, Inc.

Inventor： Takashi Ando ,  Ruqiang Bao ,  Masanobu Hatanaka ,  Vijay Narayanan ,  Yohei Ogawa ,  John Rozen

IPC: H01L29/49 ,  H01L29/43 ,  H01L27/092 ,  H01L21/285 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/775

Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.

公开(公告)号：US11031301B2

公开(公告)日：2021-06-08

申请号：US16691803

申请日：2019-11-22

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Unoh Kwon ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L29/49 ,  H01L27/092 ,  H01L21/28

Abstract: Embodiments of the invention include a wafer having gate stacks over channel fins. The wafer includes a first channel fin in an n-type region of a substrate, a second channel fin in a p-type region of the substrate, and a gate dielectric over the substrate and the first and second channel fins. A work function metal stack is over the gate dielectric, the first channel fin in the n-type region, and the second channel fin in the p-type region. The work function metal stack over the gate dielectric and the first channel fin in the n-type region forms a first work function metal stack. The work function metal stack over the gate dielectric and the second fin in the p-type region forms a second work function metal stack. The first work function metal stack includes a shared layer of work function metal shared with the second work function metal stack.

公开(公告)号：US20210118881A1

公开(公告)日：2021-04-22

申请号：US17133157

申请日：2020-12-23

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruqiang Bao ,  Dechao Guo ,  Vijay Narayanan

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/08

Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

公开(公告)号：US10957696B2

公开(公告)日：2021-03-23

申请号：US15593816

申请日：2017-05-12

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruqiang Bao ,  Dechao Guo ,  Vijay Narayanan

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

公开(公告)号：US10833150B2

公开(公告)日：2020-11-10

申请号：US16032632

申请日：2018-07-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Martin M. Frank ,  Kam-Leung Lee ,  Eduard A. Cartier ,  Vijay Narayanan ,  Jean Fompeyrine ,  Stefan Abel ,  Oleg Gluschenkov ,  Hemanth Jagannathan

IPC: H01L21/00 ,  H01L29/04 ,  H01L21/02 ,  H01L29/06 ,  H01L29/51

Abstract: A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.

公开(公告)号：US20200295147A1

公开(公告)日：2020-09-17

申请号：US16351729

申请日：2019-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： RUQIANG BAO ,  HEMANTH JAGANNATHAN ,  Paul Charles Jamison ,  Choonghyun Lee ,  Sanjay C. Mehta ,  Vijay Narayanan

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778

Abstract: A technique relates to a semiconductor device. A gate stack is formed on a fin, the gate stack being formed to have a length in a vertical direction. A gate contact is formed adjacent to the gate stack for the length of the gate stack in the vertical direction.

公开(公告)号：US10686039B2

公开(公告)日：2020-06-16

申请号：US16395024

申请日：2019-04-25

Applicant: International Business Machines Corporation

Inventor： Martin M. Frank ,  Takashi Ando ,  Xiao Sun ,  Jin Ping Han ,  Vijay Narayanan

IPC: H01L21/28 ,  H01L29/12 ,  H01L29/06 ,  H01L27/085 ,  H01L23/52 ,  H01L27/088 ,  H01L21/8234

Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.

公开(公告)号：US20200052207A1

公开(公告)日：2020-02-13

申请号：US16058428

申请日：2018-08-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Hiroyuki Miyazoe ,  Seyoung Kim ,  Vijay Narayanan

IPC: H01L45/00 ,  H01L27/24

Abstract: A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.

公开(公告)号：US10361281B2

公开(公告)日：2019-07-23

申请号：US15911892

申请日：2018-03-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Takashi Ando ,  Eduard A. Cartier ,  Kisik Choi ,  Vijay Narayanan

IPC: H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L21/321 ,  H01L21/324 ,  H01L29/423 ,  H01L21/3205

Abstract: A method of fabricating a replacement gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over the area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; depositing a sacrificial layer over the thin metal layer; performing a first rapid thermal anneal; removing the sacrificial layer; and depositing a metal layer of low resistivity metal for gap fill.