-
公开(公告)号：US20200161303A1
公开(公告)日：2020-05-21
申请号：US16691732
申请日：2019-11-22
Applicant: International Business Machines Corporation
Inventor： ZHENXING BI , Kangguo CHENG , ZHENG XU , DEXIN KONG
IPC: H01L27/092 , H01L29/20 , H01L29/78 , H01L29/10 , H01L21/8238 , H01L21/033 , H01L29/08 , H01L29/66
Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.
-
公开(公告)号：US20200161302A1
公开(公告)日：2020-05-21
申请号：US16192896
申请日：2018-11-16
Applicant: International Business Machines Corporation
Inventor： ZHENXING BI , Kangguo CHENG , ZHENG XU , DEXIN KONG
IPC: H01L27/092 , H01L29/20 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10 , H01L21/033 , H01L21/8238
Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.
-
Patent Agency Ranking
3.发明申请公开(公告)号：US20190294039A1
公开(公告)日：2019-09-26
申请号：US16441911
申请日：2019-06-14
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： CHIEH-YU LIN , DONGBING SHAO , KEHAN TIAN , ZHENG XU
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
-
公开(公告)号：US20240036074A1
公开(公告)日：2024-02-01
申请号：US17876652
申请日：2022-07-29
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： KUSHAGRA SINHA , ZHENG XU , Yufei Wu , Myra Ahmad , Nikhilesh C Sahani
CPC classification number: G01R1/06794 , G01R31/2891
Abstract: Aspect of the disclosure include a testing apparatus and a method for testing an integrated circuit. One embodiment of the testing apparatus may comprise a main probe pin configured for electrical testing of a sample, the sample having a terminal pad, and a secondary probe pin configured for contact testing of the main probe pin against the terminal pad. In some embodiments, the testing apparatus may further comprise an indicator circuit electrically connected to the main probe pin and the secondary probe pin. The indicator circuit may output a signal when the main probe pin and the secondary probe pin are in simultaneous electrical engagement with the terminal pad.
-
公开(公告)号：US20220285614A1
公开(公告)日：2022-09-08
申请号：US17192223
申请日：2021-03-04
Applicant: International Business Machines Corporation
Inventor： JUNTAO LI , Kangguo Cheng , DEXIN KONG , ZHENG XU
Abstract: An approach to form a semiconductor structure with a multiple layer phase change material stack and four electrodes that functions as an integrated switch device. The semiconductor structure includes a sidewall spacer that is on two opposing sides of the multiple layer phase change material stack contacting an edge of each layer of the multiple layer phase change material stack. The semiconductor structure includes a pair of a first type of electrode, where each of the pair of the first type of electrode abuts each of the sidewall spacers on the two opposing sides of the multiple layer phase change material stack. A pair of a second type of electrode, where each of the second type of electrode abuts each of two other opposing sides of the multiple layer phase change material stack and contacts a heater material on outside portions of the multiple layer phase change material stack.
-
6.发明申请公开(公告)号：US20190072846A1
公开(公告)日：2019-03-07
申请号：US15819213
申请日：2017-11-21
Inventor： CHIEH-YU LIN , DONGBING SHAO , KEHAN TIAN , ZHENG XU
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
-
7.发明申请公开(公告)号：US20190072845A1
公开(公告)日：2019-03-07
申请号：US15696505
申请日：2017-09-06
Inventor： CHIEH-YU LIN , DONGBING SHAO , KEHAN TIAN , ZHENG XU
CPC classification number: G03F1/36 , G03F1/38 , G03F1/70 , G06F17/5009 , G06F17/5081 , G06F2217/12
Abstract: Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.
-
-
-
-
-
-
Search Results
7
records
(took 0.016 seconds)
