公开(公告)号：US20230169032A1

公开(公告)日：2023-06-01

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20200334196A1

公开(公告)日：2020-10-22

申请号：US16917888

申请日：2020-06-30

Applicant: Intel Corporation

Inventor： NEVINE NASSIF ,  YEN-CHENG LIU ,  KRISHNAKANTH V. SISTLA ,  GERALD PASDAST ,  SIVA SOUMYA EACHEMPATI ,  TEJPAL SINGH ,  ANKUSH VARMA ,  MAHESH K. KUMASHIKAR ,  SRIKANTH NIMMAGADDA ,  CARLETON L. MOLNAR ,  VEDARAMAN GEETHA ,  JEFFREY D. CHAMBERLAIN ,  WILLIAM R. HALLECK ,  GEORGE Z. CHRYSOS ,  JOHN R. AYERS ,  DHEERAJ R. SUBBAREDDY

IPC: G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20170115716A1

公开(公告)日：2017-04-27

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： ANKUSH VARMA ,  KRISHNAKANTH V. SISTLA ,  MARTIN T. ROWLAND ,  CHRIS POIRIER ,  ERIC J. DEHAEMER ,  AVINASH N. ANANTHAKRISHNAN ,  JEREMY J. SHRALL ,  XIUTING C. MAN ,  STEPHEN H. GUNTHER ,  KRISHNA K. RANGAN ,  DEVADATTA V. BODAS ,  DON SOLTIS ,  HANG T. NGUYEN ,  CYPRIAN W. WOO ,  THI DANG

IPC: G06F1/28 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

公开(公告)号：US20230236651A1

公开(公告)日：2023-07-27

申请号：US18007627

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： UJJWAL GUPTA ,  ANKUSH VARMA ,  LAKSHMIPRIYA SESHAN ,  NIKETHAN SHIVANAND BALIGAR ,  NIKHIL GUPTA ,  SWADESH CHOUDHARY ,  YOGESH BANSAL

IPC: G06F1/324 ,  G06F1/10 ,  G06F11/34

CPC classification number: G06F1/324 ,  G06F1/10 ,  G06F11/3409

Abstract: A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

公开(公告)号：US20210018971A1

公开(公告)日：2021-01-21

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： EFRAIM ROTEM ,  ELIEZER WEISSMANN ,  ERIC DEHAEMER ,  ALEXANDER GENDLER ,  NADAV SHULMAN ,  KRISHNAKANTH SISTLA ,  NIR ROSENZWEIG ,  ANKUSH VARMA ,  ARIEL SZAPIRO ,  ARYE ALBAHARI ,  IDO MELAMED ,  NIR MISGAV ,  VIVEK GARG ,  NIMROD ANGEL ,  ADWAIT PURANDARE ,  ELKANA KOREM

IPC: G06F1/329 ,  G06F1/3206 ,  G06F9/48 ,  G06F9/30 ,  G06F9/4401

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20160378486A1

公开(公告)日：2016-12-29

申请号：US14750212

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： ANKUSH VARMA ,  KRISTOFFER D. FLEMING ,  EUGENE GORBATOV ,  ROBERT E. GOUGH ,  KRISHNAKANTH V. SISTLA

IPC: G06F9/30 ,  G06F9/48

CPC classification number: G06F9/4893 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/455

Abstract: An apparatus and method for performing high performance instruction emulation. For example, one embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-powered instructions if the number of high-power instructions are below the specified threshold.

Abstract translation: 一种用于执行高性能指令仿真的装置和方法。 例如，本发明的一个实施例包括处理包括大功率和标准指令的指令集的处理器，包括：分析模块，用于确定指定窗口内的多个高功率指令是否高于或低于指定阈值; 执行模式选择模块，如果大功率指令的数量高于规定的阈值，则选择大功率指令的本地执行，或者如果大功率指令的数量是大功率指令的数量，则选择高功率指令的仿真执行 低于规定的阈值。