公开(公告)号：US20220270978A1

公开(公告)日：2022-08-25

申请号：US17742792

申请日：2022-05-12

Applicant: Intel Corporation

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US10727183B2

公开(公告)日：2020-07-28

申请号：US16559086

申请日：2019-09-03

Applicant: Intel Corporation

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US10446493B2

公开(公告)日：2019-10-15

申请号：US15477506

申请日：2017-04-03

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528 ,  H01L23/522

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US09876113B2

公开(公告)日：2018-01-23

申请号：US15220304

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L21/78 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US09680016B2

公开(公告)日：2017-06-13

申请号：US15220355

申请日：2016-07-26

Applicant: Intel Corporation

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A. Glass ,  Thomas Hoffmann

IPC: H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167 ,  H01L29/36 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US09627321B2

公开(公告)日：2017-04-18

申请号：US14675613

申请日：2015-03-31

Applicant: Intel Corporation

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel. The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US20170011998A1

公开(公告)日：2017-01-12

申请号：US15276385

申请日：2016-09-26

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

公开(公告)号：US20170207120A1

公开(公告)日：2017-07-20

申请号：US15477506

申请日：2017-04-03

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: At least one conductive line in a dielectric layer over a substrate is recessed to form a channel. The channel is self-aligned to the conductive line. The channel can be formed by etching the conductive line to a predetermined depth using a chemistry comprising an inhibitor to provide uniformity of etching independent of a crystallographic orientation. A capping layer to prevent electromigration is deposited on the recessed conductive line in the channel The channel is configured to contain the capping layer within the width of the conductive line.

公开(公告)号：US09455224B2

公开(公告)日：2016-09-27

申请号：US14746315

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

IPC: H01L21/76 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。

公开(公告)号：US20150294935A1

公开(公告)日：2015-10-15

申请号：US14746315

申请日：2015-06-22

Applicant: INTEL CORPORATION

Inventor： Boyan Boyanov ,  Kanwal Jit Singh ,  James Clarke ,  Alan Myers

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etchstop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etchstop layer, and an interconnect feature may pass through the second insulator layer and the conformal etchstop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Abstract translation: 公开了能够改善未上行的导电互连特征与相邻导电特征之间的短路裕度的技术。 在一些实施例中，可以将蚀刻施加到其中具有一个或多个导电特征的绝缘体层，使得绝缘体层凹入导电特征的顶部下方，并且导电特征的边缘被倒圆或以其它方式软化。 然后可以在导电特征和绝缘体材料上沉积保形蚀刻层。 可以在保形蚀刻阻挡层上方沉积第二绝缘体层，并且互连特征可以穿过第二绝缘体层和保形蚀刻阻挡层以与导电特征之一的圆形部分连接。 在一些实施例中，互连特征是未上通孔，并且通孔的未上覆部分可以穿透或不穿透保形阻挡层。