公开(公告)号：US20170069725A1

公开(公告)日：2017-03-09

申请号：US15122796

申请日：2014-06-26

Applicant: Intel Corporation

Inventor： GOPINATH BHIMARASETTI ,  WALID M. HAFEZ ,  JOODONG PARK ,  WEIMIN HAN ,  RAYMOND E. COTNER ,  CHIA-HONG JAN

IPC: H01L29/36 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/36 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7853

Abstract: Non-planar semiconductor devices having omega-fins with doped sub-fin regions and methods of fabricating non-planar semiconductor devices having omega-fins with doped sub-fin regions are described. For example, a semiconductor device includes a plurality of semiconductor fins disposed above a semiconductor substrate, each semiconductor fin having a sub-fin portion below a protruding portion, the sub-fin portion narrower than the protruding portion. A solid state dopant source layer is disposed above the semiconductor substrate, conformal with the sub-fin region but not the protruding portion of each of the plurality of semiconductor fins. An isolation layer is disposed above the solid state dopant source layer and between the sub-fin regions of the plurality of semiconductor fins. A gate stack is disposed above the isolation layer and conformal with the protruding portions of each of the plurality of semiconductor fins.

Abstract translation: 描述了具有掺杂子鳍区域的ω鳍片的非平面半导体器件以及制造具有掺杂子鳍片区域的具有Ω形翅片的非平面半导体器件的方法。 例如，半导体器件包括设置在半导体衬底上方的多个半导体鳍片，每个半导体鳍片具有在突出部分下方的副鳍片部分，子鳍片部分比突出部分窄。 固态掺杂剂源层设置在半导体衬底之上，与子鳍区域共形而不是多个半导体鳍片中的每一个的突出部分。 隔离层设置在固态掺杂剂源层上方和多个半导体鳍片的子鳍片区域之间。 栅极叠层设置在隔离层上方并与多个半导体鳍片中的每一个的突起部分保形。

公开(公告)号：US20160197082A1

公开(公告)日：2016-07-07

申请号：US14912890

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： JOODONG PARK ,  GOPINATH BHIMARASETTI ,  RAHUL RAMASWAMY ,  CHIA-HONG JAN ,  WALID M. HAFEZ ,  JENG-YA D. YEH ,  CURTIS TSAI

IPC: H01L27/108

CPC classification number: H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

Abstract: Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

Abstract translation: 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和用于制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方并且包括设置在两个宽鳍片区域之间的窄鳍区域的半导体鳍片。 栅电极堆叠被配置为与半导体鳍片的窄鳍区域共形，栅电极堆叠包括设置在栅介质层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍片的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域布置在相应的一个宽鳍片区域中。

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.