中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.011 seconds)

    Three dimensional memory structure
    5.
    发明授权
    Three dimensional memory structure 有权
    三维记忆结构

    公开(公告)号：US09129859B2

    公开(公告)日：2015-09-08

    申请号：US13786925

    申请日：2013-03-06

    Applicant: Intel Corporation

    Inventor： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

    IPC: H01L29/76 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

    Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。

    Stacked thin channels for boost and leakage improvement
    8.
    发明授权
    Stacked thin channels for boost and leakage improvement 有权
    堆叠薄通道，用于提升和泄漏改善

    公开(公告)号：US09209199B2

    公开(公告)日：2015-12-08

    申请号：US14222070

    申请日：2014-03-21

    Applicant: Intel Corporation

    Inventor： Fatma Arzum Simsek-Ege ,  Jie Jason Sun ,  Benben Li ,  Srikant Jayanti ,  Han Zhao ,  Guangyu Huang ,  Haitao Liu

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/66 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/02

    CPC classification number: H01L29/105 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/16

    Abstract: A hollow-channel memory device comprises a source layer, a first hollow-channel pillar structure formed on the source layer, and a second hollow-channel pillar structure formed on the first hollow-channel pillar structure. The first hollow-channel pillar structure comprises a first thin channel and the second hollow-channel pillar structure comprises a second thin channel that is in contact with the first thin channel. In one exemplary embodiment, the first thin channel comprises a first level of doping; and the second thin channel comprises a second level of doping that is different from the first level of doping. In another exemplary embodiment, the first and second levels of doping are the same.

    Abstract translation: 中空通道存储器件包括源极层，形成在源极层上的第一中空沟槽柱结构以及形成在第一中空通道柱结构上的第二中空沟槽柱结构。 第一中空通道柱结构包括第一细通道，第二中空通道柱结构包括与第一薄通道接触的第二细通道。 在一个示例性实施例中，第一薄沟道包括第一级掺杂; 并且第二薄沟道包括与第一掺杂水平不同的第二掺杂水平。 在另一示例性实施例中，第一和第二级掺杂是相同的。

    THREE DIMENSIONAL MEMORY STRUCTURE
    9.
    发明申请
    THREE DIMENSIONAL MEMORY STRUCTURE 审中-公开
    三维存储器结构

    公开(公告)号：US20150333085A1

    公开(公告)日：2015-11-19

    申请号：US14813398

    申请日：2015-07-30

    Applicant: Intel Corporation

    Inventor： Haitao Liu ,  Chandra V. Mouli ,  Krishna K. Parat ,  Jie Sun ,  Guangyu Huang

    IPC: H01L27/115 ,  H01L29/04 ,  G11C16/06 ,  H01L29/16

    CPC classification number: H01L27/11582 ,  G11C16/06 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A method to fabricate a three dimensional memory structure includes forming an array stack, creating a layer of sacrificial material above the array stack, etching a hole through the layer of sacrificial material and the array stack, creating a pillar of semiconductor material in the hole to form at least two vertically stacked flash memory cells that use the pillar as a common body, removing at least some of the layer of sacrificial material around the pillar to expose a portion of the pillar, and forming a field effect transistor (FET) using the portion of the pillar as the body of the FET.

    Abstract translation: 制造三维存储器结构的方法包括形成阵列堆叠，在阵列堆叠上方产生牺牲材料层，蚀刻通过牺牲材料层和阵列堆叠的孔，在孔中产生半导体材料的柱 形成使用该柱作为共同体的至少两个垂直堆叠的闪存单元，去除柱周围的牺牲材料层中的至少一部分以暴露柱的一部分，以及使用该场效应晶体管 柱的一部分作为FET的主体。

Patent Agency Ranking