公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US20230187386A1

公开(公告)日：2023-06-15

申请号：US17550236

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  John S. Guzek ,  Hamid Azimi

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L23/645 ,  H01L24/16 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49838 ,  H01L28/10 ,  H01L2224/16227 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a first surface and an opposing second surface, the second surface having a cavity; a first die at least partially nested in the cavity; an insulating material on the second surface of the substrate, the insulating material having a first surface and an opposing second surface, wherein the first surface of the insulating material is at the second surface of the substrate; a planar inductor embedded in the insulating material, the planar inductor including a thin film at least partially surrounding a conductive trace; and a second die, at the second surface of the insulating material, electrically coupled to the first die.

公开(公告)号：US20240096809A1

公开(公告)日：2024-03-21

申请号：US17932624

申请日：2022-09-15

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Robert Alan May ,  Onur Ozkan ,  Ali Lehaf ,  Steve Cho ,  Gang Duan ,  Jieping Zhang ,  Rahul N. Manepalli ,  Ravindranath Vithal Mahajan ,  Hamid Azimi

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/5383 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L24/32 ,  H01L2224/13082 ,  H01L2224/1403 ,  H01L2224/16238 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/2201 ,  H01L2224/32225

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a surface including first conductive contacts and second conductive contacts, wherein the first conductive contacts have a first thickness and the second conductive contacts have a second thickness different than the first thickness; a first microelectronic component having third conductive contacts, wherein respective ones of the third conductive contacts are coupled to respective ones of the first conductive contacts by first interconnects, wherein the first interconnects include solder having a thickness between 2 microns and 35 microns; and a second microelectronic component having fourth conductive contact, wherein respective ones of the fourth conductive contacts are coupled to respective ones of the second conductive contacts by second interconnects, wherein the second interconnects include solder having a thickness between 5 microns and 50 microns.

公开(公告)号：US20230197697A1

公开(公告)日：2023-06-22

申请号：US17552581

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Srinivas V. Pietambaram ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  John S. Guzek ,  Hamid Azimi

IPC: H01L25/16 ,  H01L23/15 ,  H01L23/498 ,  H01L49/02 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L23/15 ,  H01L23/49827 ,  H01L28/60 ,  H01L23/49811 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a glass substrate, having a surface, including a through-glass-substrate via (TGV) and a cavity on the surface; a first die nested in the cavity; an insulating material on the surface of the glass substrate; a first conductive pillar and a second conductive pillar through the insulating material; a capacitor, in the insulating material, including a first conductive layer, on the surface of the glass substrate, electrically coupled to the TGV and the first conductive pillar forming a first plate of the capacitor, a dielectric layer on the first conductive layer; and a second conductive layer, on the dielectric layer, electrically coupled to the second conductive pillar forming a second plate of the capacitor; and a second die, on the insulating material, electrically coupled to the first die.

公开(公告)号：US10306760B2

公开(公告)日：2019-05-28

申请号：US15497156

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Yonggang Li ,  Islam Salama ,  Charan Gurumurthy ,  Hamid Azimi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18

Abstract: A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.