公开(公告)号：US20230069054A1

公开(公告)日：2023-03-02

申请号：US17410257

申请日：2021-08-24

Applicant: Intel Corporation

Inventor： Souvik GHOSH ,  Han Wui THEN ,  Pratik KOIRALA ,  Tushar TALUKDAR ,  Paul NORDEEN ,  Nityan NAIR ,  Marko RADOSAVLJEVIC ,  Ibrahim BAN ,  Kimin JUN ,  Jay GUPTA ,  Paul B. FISCHER ,  Nicole K. THOMAS ,  Thomas HOFF ,  Samuel James BADER

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/66

Abstract: Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

公开(公告)号：US20190386007A1

公开(公告)日：2019-12-19

申请号：US16452469

申请日：2019-06-25

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/51 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/12

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20190035790A1

公开(公告)日：2019-01-31

申请号：US16151175

申请日：2018-10-03

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/16 ,  H01L29/06 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20240213140A1

公开(公告)日：2024-06-27

申请号：US18088541

申请日：2022-12-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Samuel James BADER ,  Ahmad ZUBAIR ,  Pratik KOIRALA ,  Michael S. BEUMER ,  Heli Chetanbhai VORA ,  Ibrahim BAN ,  Nityan NAIR ,  Thomas HOFF

IPC: H01L23/522 ,  H01L23/48

CPC classification number: H01L23/5223 ,  H01L23/481 ,  H01L23/5226

Abstract: Structures having backside high voltage capacitors for front side GaN-based devices are described. In an example, an integrated circuit structure includes a front side structure including a GaN-based device layer, and one or more metallization layers above the GaN-based device layer. A backside structure is below and coupled to the GaN-based layer, the backside structure including metal layers and one or more alternating laterally-recessed metal insulator metal capacitors.

公开(公告)号：US20180226407A1

公开(公告)日：2018-08-09

申请号：US15727918

申请日：2017-10-09

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L27/10802 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823857 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0924 ,  H01L27/0928 ,  H01L27/108 ,  H01L27/10826 ,  H01L27/10844 ,  H01L27/10879 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/785 ,  H01L29/7851 ,  Y10S257/903

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20220093683A1

公开(公告)日：2022-03-24

申请号：US17031719

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Ibrahim BAN ,  Paul B. FISCHER ,  Kimin JUN ,  Paul NORDEEN ,  Pratik KOIRALA ,  Tushar TALUKDAR

IPC: H01L27/20 ,  H01L29/16 ,  H01L29/20 ,  H03H9/02 ,  H03H9/17 ,  H03H9/54 ,  H03H9/56

Abstract: Embodiments disclosed herein include resonators and methods of forming such resonators. In an embodiment a resonator comprises a substrate, where a cavity is disposed into a surface of the substrate, and a piezoelectric film suspended over the cavity. In an embodiment, the piezoelectric film has a first surface and a second surface opposite from the first surface, and the piezoelectric film is single crystalline and has a thickness that is 0.5 μm or less. In an embodiment a first electrode is over the first surface of the piezoelectric film, and a second electrode is over the second surface of the piezoelectric film.

公开(公告)号：US20210159228A1

公开(公告)日：2021-05-27

申请号：US17142176

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20200312854A1

公开(公告)日：2020-10-01

申请号：US16900359

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Peter L.D. CHANG ,  Uygar E. AVCI ,  David KENCKE ,  Ibrahim BAN

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

Abstract: A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US20240222440A1

公开(公告)日：2024-07-04

申请号：US18089919

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Samuel James BADER ,  Han Wui THEN ,  Ibrahim BAN ,  Heli Chetanbhai VORA ,  Marko RADOSAVLJEVIC

IPC: H01L29/267 ,  H01L21/02 ,  H01L21/18 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/0254 ,  H01L21/185 ,  H01L21/32051 ,  H01L29/0607 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for using layer transfer techniques to bond a silicon layer with a GaN layer, where the silicon layer includes a first portion of a device, for example a transistor, and the GaN layer includes a second portion of the device. Other embodiments may be described and/or claimed.

公开(公告)号：US20230054719A1

公开(公告)日：2023-02-23

申请号：US17408025

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Souvik GHOSH ,  Paul NORDEEN ,  Tushar TALUKDAR ,  Thomas HOFF ,  Ibrahim BAN ,  Kimin JUN ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Paul B. FISCHER ,  Han Wui THEN

IPC: H01L29/778 ,  H01L29/20

Abstract: Gallium nitride (GaN) layer transfer and regrowth for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate. An insulator layer is over the substrate. A device layer is directly on the insulator layer. The device layer has a thickness of less than approximately 500 nanometers.