公开(公告)号：US20210200675A1

公开(公告)日：2021-07-01

申请号：US16727657

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Ravi K. VENKATESAN ,  Shlomi SHUA ,  Oz SHITRIT ,  Michael BEHAR ,  Roni ROSNER

IPC: G06F12/084 ,  G06F12/126

Abstract: Disclosed embodiments relate to a shared read request (SRR) using a common request tracker (CRT) as a temporary cache. In one example, a multi-core system includes a memory and a memory controller to receive a SRR from a core when a Leader core is not yet identified, allocate a CRT entry and store the SRR therein, mark it as a Leader, send a read request to a memory address indicated by the SRR, and when read data returns from the memory, store the read data in the CRT entry, send the read data to the Leader core, and await receipt, unless already received, of another SRR from a Follower core, the other SRR having a same address as the SRR, then, send the read data to the Follower core, and deallocate the CRT entry.

公开(公告)号：US20210056030A1

公开(公告)日：2021-02-25

申请号：US17092093

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128 ,  G06F12/121 ,  G06F12/0886

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20180189192A1

公开(公告)日：2018-07-05

申请号：US15394550

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Israel DIAMAND ,  Zvika GREENFIELD ,  Julius MANDELBLAT ,  Asaf RUBINSTEIN

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/0893

CPC classification number: G06F12/0893 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/507 ,  G06F2212/608

Abstract: An apparatus is described. The apparatus includes a memory controller to interface to a multi-level system memory having first and second different cache structures. The memory controller has circuitry to service a read request by concurrently performing a look-up into the first and second different cache structures for a cache line that is targeted by the read request.

公开(公告)号：US20190095331A1

公开(公告)日：2019-03-28

申请号：US15717939

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Israel DIAMAND ,  Alaa R. ALAMELDEEN ,  Sreenivas SUBRAMONEY ,  Supratik MAJUMDER ,  Srinivas Santosh Kumar MADUGULA ,  Jayesh GAUR ,  Zvika GREENFIELD ,  Anant V. NORI

IPC: G06F12/0846 ,  G06F12/0811 ,  G06F12/128

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

公开(公告)号：US20190042131A1

公开(公告)日：2019-02-07

申请号：US15940499

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Lakshminarayana PAPPU ,  Christopher E. COX ,  Navneet DOUR ,  Asaf RUBINSTEIN ,  Israel DIAMAND

IPC: G06F3/06 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/42

Abstract: In a computer system, a multilevel memory includes a near memory device and a far memory device, which are byte addressable. The multilevel memory includes a controller that receives a data request including original tag information. The controller includes routing hardware to selectively provide alternate tag information for the data request to cause a cache hit or a cache miss to selectively direct the request to the near memory device or to the far memory device, respectively. The controller can include selection circuitry to select between the original tag information and the alternate tag information to control where the data request is sent.

公开(公告)号：US20180285271A1

公开(公告)日：2018-10-04

申请号：US15476798

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Zvika GREENFIELD ,  Zeshan A. CHISHTI ,  Israel DIAMAND

IPC: G06F12/0831 ,  G06F12/128 ,  G06F12/0891 ,  G06F12/0868 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/123

CPC classification number: G06F12/0831 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/121 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/608 ,  G06F2212/69

Abstract: Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction watermark, an eviction process is triggered for evicting a superline from a sectored cache storing at least one superline. An eviction candidate is selected from superlines that have: 1) a sector usage below or equal to a superline low watermark and 2) an RT timestamp that is greater than a superline age watermark.