公开(公告)号：US11901400B2

公开(公告)日：2024-02-13

申请号：US16369737

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01L49/02 ,  H01G4/012 ,  H01G4/30 ,  H01L23/522 ,  H10B51/00

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed that includes a first metal layer and a seed layer on the first metal layer. The seed layer includes a polar phase crystalline structure. The capacitor also includes a ferroelectric layer on the seed layer and a second metal layer on the ferroelectric layer.

公开(公告)号：US12119387B2

公开(公告)日：2024-10-15

申请号：US17033471

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Nazila Haratipour ,  Siddharth Chouksey ,  Jack T. Kavalieros ,  Jitendra Kumar Jha ,  Matthew V. Metz ,  Mengcheng Lu ,  Anand S. Murthy ,  Koustav Ganguly ,  Ryan Keech ,  Glenn A. Glass ,  Arnab Sen Gupta

IPC: H01L29/45 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Low resistance approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is directly on the first or second semiconductor source or drain structure, the source or drain contact including a barrier layer and an inner conductive structure.

公开(公告)号：US10079266B2

公开(公告)日：2018-09-18

申请号：US15122129

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Anant H. Jahagirdar ,  Mengcheng Lu

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US11769789B2

公开(公告)日：2023-09-26

申请号：US16368450

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01G4/30 ,  H10B51/00 ,  H01L23/522 ,  H01L49/02 ,  H01G4/012

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.