公开(公告)号：US11984317B2

公开(公告)日：2024-05-14

申请号：US17308813

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Marie Krysak ,  James Blackwell ,  Lauren Doyle ,  Brian Zaccheo ,  Patrick Theofanis ,  Michael Robinson ,  Florian Gstrein

IPC: H01L21/027 ,  G03F7/004 ,  G03F7/20 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/0274 ,  G03F7/0042 ,  H01L21/76877 ,  H01L23/5226 ,  G03F7/2004

Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

公开(公告)号：US20220199816A1

公开(公告)日：2022-06-23

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US11737368B2

公开(公告)日：2023-08-22

申请号：US16367136

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Michael Robinson ,  Huiying Liu

IPC: H10N50/01 ,  H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.

公开(公告)号：US20210375616A1

公开(公告)日：2021-12-02

申请号：US17308813

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Marie Krysak ,  James Blackwell ,  Lauren Doyle ,  Brian Zaccheo ,  Patrick Theofanis ,  Michael Robinson ,  Florian Gstrein

IPC: H01L21/027 ,  G03F7/004 ,  H01L23/522 ,  H01L21/768

Abstract: Techniques, structures, and materials related to extreme ultraviolet (EUV) lithography are discussed. Multiple patterning inclusive of first patterning a grating of parallel lines and second patterning utilizing EUV lithography to form plugs in the grating, and optional trimming of the plugs may be employed. EUV resists, surface treatments, resist additives, and optional processing inclusive of plug healing, angled etch processing, electric field enhanced post exposure bake are described, which provide improved processing reliability, feature definition, and critical dimensions.

公开(公告)号：US12224337B2

公开(公告)日：2025-02-11

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US20240201586A1

公开(公告)日：2024-06-20

申请号：US18068732

申请日：2022-12-20

Applicant: Intel Corporation

Inventor： James Blackwell ,  Charles Cameron Mokhtarzadeh ,  Lauren Elizabeth Doyle ,  Eric Mattson ,  Patrick Theofanis ,  John J. Plombon ,  Michael Robinson ,  Marie Krysak ,  Paul Meza-Morales ,  Scott Semproni ,  Scott B. Clendenning

IPC: G03F7/004 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38

CPC classification number: G03F7/0042 ,  G03F7/038 ,  G03F7/167 ,  G03F7/2004 ,  G03F7/38

Abstract: Precursors and methods related to a tin-based photoresist are disclosed herein. In some embodiments, a method for forming a tin-based photoresist may include exposing a tin-containing precursor and a co-reagent to a substrate to form a photoresist having tin clusters; selectively exposing the photoresist to extreme ultraviolet radiation (EUV); and exposing the photoresist to heat to form, in the region, crosslinking between the tin clusters. In some embodiments, the precursor has a formula R1R2Sn(N(CH3)2)2, and R1 and R2 are selected from the group consisting of neo-silyl, neo-pentyl, phenyl, benzyl, methyl-bis(trimethylsilyl), methyl, ethyl, isopropyl, tert-butyl, n-butyl, N,N-dimethylpropylamine, and N, N-dimethlybutylamine. In other embodiments, the precursor includes a chelating alkyl-amine or alkyl-amide ligand featuring a 5 membered or 6 membered tin-based heterocycle bound κ2-C,N with an alkyl group on the ligand backbone, wherein the alkyl group includes methyl, ethyl, vinyl, hydrogen, or tert-butyl.

公开(公告)号：US10943950B2

公开(公告)日：2021-03-09

申请号：US16367126

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Aaron Littlejohn ,  Michael Robinson ,  Huiying Liu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.

公开(公告)号：US20200312907A1

公开(公告)日：2020-10-01

申请号：US16367126

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Aaron Littlejohn ,  Michael Robinson ,  Huiying Liu

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01F10/32 ,  H01L43/12 ,  G11C11/16 ,  H01F41/34

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode, a magnetic junction on the conductive layer and a second electrode above the magnetic junction. The magnetic junction includes a magnetic structure including a first magnetic layer including cobalt, a non-magnetic layer including platinum or tungsten on the first magnetic layer and a second magnetic layer including cobalt on the non-magnetic layer. The magnetic junction further includes an anti-ferromagnetic layer on the magnet structure, a fixed magnet above the anti-ferromagnetic layer, a free magnet above the fixed magnet and a tunnel barrier between the fixed magnet and the free magnet.

公开(公告)号：US20200313084A1

公开(公告)日：2020-10-01

申请号：US16367136

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Daniel Ouellette ,  Christopher Wiegand ,  Justin Brockman ,  Tofizur Rahman ,  Oleg Golonzka ,  Angeline Smith ,  Andrew Smith ,  James Pellegren ,  Michael Robinson ,  Huiying Liu

IPC: H01L43/12 ,  H01L27/22

Abstract: A memory device includes a first electrode, a conductive layer including iridium above the first electrode and a magnetic junction directly on the conductive layer. The magnetic junction further includes a pinning structure above the conductive layer, a fixed magnet above the pinning structure, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier layer and a second electrode above the free magnet. The conductive layer including iridium and the pinning structure including iridium provide switching efficiency.