公开(公告)号：US20240160570A1

公开(公告)日：2024-05-16

申请号：US17988626

申请日：2022-11-16

Applicant: Intel Corporation

Inventor： George Leonard TKACHUK ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Youngsoo CHOI ,  Chitra NATARAJAN ,  Prasad GHATIGAR ,  Shrikant M. SHAH

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/62

Abstract: Mechanisms to identify key sections of input-output (IO) packets and use for efficient IO caching and associated apparatus and methods. Data, such as packets, are received from an IO device coupled to an IO port on a processor including a cache domain including multiple caches, such as L1/L2 and L3 or Last Level Cache (LLC). The data are logically partitioned into cache lines and embedded logic on the processor is used to identify one or more important cache lines using a cache importance pattern. Cache lines that are identified as important are written to a cache or a first cache level, while unimportant cache lines are written to memory or a second cache level that is higher than the first cache level. Software running on one or more processor cores may be used to program cache importance patterns for one or more data types or transaction types.

公开(公告)号：US20190042331A1

公开(公告)日：2019-02-07

申请号：US16131728

申请日：2018-09-14

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Zhu ZHOU ,  John MANGAN

IPC: G06F9/50 ,  G06F1/32

Abstract: Examples may include a method of power aware load balancing in a computing platform. The method includes computing a number of enabled worker cores to process an expected traffic of received packets. A number of active consumer queues is adjusted based at least in part on the number of enabled worker cores, with consumer queues being associated with worker cores. A worker core polls the consumer queue associated with the worker core, gets and processes a packet descriptor describing a received packet from the consumer queue based on the consumer queue being not empty, and enters a low power state when the consumer queue is empty and pends on a new packet descriptor being entered into the consumer queue.

公开(公告)号：US20230418655A1

公开(公告)日：2023-12-28

申请号：US18207870

申请日：2023-06-09

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/383 ,  G06F9/3004 ,  G06F9/30036

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20220164218A1

公开(公告)日：2022-05-26

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffrey J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20190317802A1

公开(公告)日：2019-10-17

申请号：US16448860

申请日：2019-06-21

Applicant: Intel Corporation

Inventor： Alexander BACHMUTSKY ,  Andrew J. HERDRICH ,  Patrick CONNOR ,  Raghu KONDAPALLI ,  Francesc GUIM BERNAT ,  Scott P. DUBAL ,  James R. HEARN ,  Kapil SOOD ,  Niall D. MCDONNELL ,  Matthew J. ADILETTA

IPC: G06F9/48 ,  G06F9/50

Abstract: Examples are described herein that can be used to offload a sequence of work events to one or more accelerators to a work scheduler. An application can issue a universal work descriptor to a work scheduler. The universal work descriptor can specify a policy for scheduling and execution of one or more work events. The universal work descriptor can refer to one or more work events for execution. The work scheduler can, in some cases, perform translation of the universal work descriptor or a work event descriptor for compatibility and execution by an accelerator. The application can receive notice of completion of the sequence of work from the work scheduler or an accelerator.

公开(公告)号：US20190075063A1

公开(公告)日：2019-03-07

申请号：US16177262

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Bruce RICHARDSON ,  John MANGAN ,  Harry VAN HAAREN ,  Ciara LOFTUS ,  Brian A. KEATING

IPC: H04L12/931 ,  H04L12/861 ,  G06F9/54 ,  G06F13/10

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

公开(公告)号：US20250123881A1

公开(公告)日：2025-04-17

申请号：US18927065

申请日：2024-10-25

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffry J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20240160568A1

公开(公告)日：2024-05-16

申请号：US17987773

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Kapil SOOD ,  Lokpraveen MOSUR ,  Aneesh AGGARWAL ,  Niall D. MCDONNELL ,  Chitra NATARAJAN ,  Ritu GUPTA ,  Edwin VERPLANKE ,  George Leonard TKACHUK

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Examples include techniques associated with data movement to a cache in a disaggregated die system. Examples include circuitry at a first die receiving and granting requests to move data to a first cache resident on the first die or to a second cache resident on a second die that also includes a core of a processor. The granting of the request based, at least in part, on a traffic source type associated with a source of the request.

公开(公告)号：US20230401109A1

公开(公告)日：2023-12-14

申请号：US18237860

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Niall D. MCDONNELL ,  Ambalavanar ARULAMBALAM ,  Te Khac MA ,  Surekha PERI ,  Pravin PATHAK ,  James CLEE ,  An YAN ,  Steven POLLOCK ,  Bruce RICHARDSON ,  Vijaya Bhaskar KOMMINENI ,  Abhinandan GUJJAR

IPC: G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5038

Abstract: Examples described herein relate to a load balancer that is configured to selectively perform ordering of requests from the one or more cores, allocate the requests into queue elements prior to allocation to one or more receiver cores of the one or more cores to process the requests, and perform two or more operations of: adjust a number of queues associated with a core of the one or more cores by changing a number of consumer queues (CQs) allocated to a single domain, adjust a number of target cores in a group of target cores to be load balanced, and order memory space writes from multiple caching agents (CAs).

公开(公告)号：US20220214973A1

公开(公告)日：2022-07-07

申请号：US17707010

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Bruce RICHARDSON ,  Niall D. MCDONNELL ,  Subhiksha RAVISUNDAR

IPC: G06F12/0891 ,  G06F12/0842 ,  G06F12/0808 ,  G06F9/38

Abstract: Examples described herein relate to a device issuing a single command to request invalidation of multiple cache lines associated with a memory address range in a cache device. In some examples, the cache device is associated with the processor. In some examples, the processor comprises one or more of a central processing unit (CPU), core, or graphics processing unit (GPU).