公开(公告)号：US10720407B2

公开(公告)日：2020-07-21

申请号：US16210540

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Ranjul Balakrishnan

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/13

Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.

公开(公告)号：US11363717B2

公开(公告)日：2022-06-14

申请号：US17090949

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ranjul Balakrishnan

IPC: H05K1/18 ,  H05K1/16

Abstract: For circuit boards that may be used in computing devices, a horizontal inductor, or an array of such inductors, may be coupled to a circuit board having a plurality of signal routing lines in a second layer from a surface of the circuit board and the horizontal inductor is positioned over these signal routing lines and may generate magnetic field lines that directionally follow the signal routing lines. The horizontal inductor may have a coiled wire with a central axis that is oriented horizontally with the surface of the circuit board. The horizontal inductor, or an array of such inductors, may be coupled to a support board attached to the circuit board.

公开(公告)号：US20200273765A1

公开(公告)日：2020-08-27

申请号：US16286736

申请日：2019-02-27

Applicant: INTEL CORPORATION

Inventor： Yogasundaram Chandiran ,  Geejagaaru Krishnamurthy Sandesh ,  Pradeep Ramesh ,  Ranjul Balakrishnan

IPC: H01L23/31 ,  H01L23/498 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

Abstract: A PCB having a first surface and a second surface includes a trench extending through the PCB, a plurality of conductive traces on one or more sidewalls of the trench. The plurality of conductive traces extends through the PCB and may be arranged in pairs across from one another along at least a portion of the length of the trench. A first set of conductive contacts are arranged in a first zig-zag pattern around a perimeter of the trench. A second set of conductive contacts are arranged in a second zig-zag pattern around the perimeter of the trench. In some cases, the first and second zig-zag patterns are arranged with respect to one another around the perimeter of the trench in an alternating fashion. A chip package is also disclosed having a pin arrangement that couples to the corresponding arrangement of conductive contacts on the PCB.

公开(公告)号：US20230317680A1

公开(公告)日：2023-10-05

申请号：US17707340

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Prabhat Ranjan ,  Boon Ping Koh ,  Min Suet Lim ,  Yew San Lim ,  Ranjul Balakrishnan ,  Omkar Karhade ,  Robert A. Stingel ,  Nitin Deshpande

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/49 ,  H01L24/48 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2224/49176 ,  H01L2224/48097 ,  H01L2224/85986

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes one or more ribbon bond connections along with one or more wire bond connections. In one example, ribbon bond connections are shown, and are coupled to ground, and configured to provide a shielding effect to wire bond connections.

公开(公告)号：US20220015246A1

公开(公告)日：2022-01-13

申请号：US17482356

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Sandesh G. Krishnamurthy ,  Jackson C.P. Kong

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K1/18

Abstract: Technologies for shielding an inductor on a circuit board are disclosed. In the illustrative embodiments, a circuit board has a voltage regulator on top of it and one or more signal traces routed beneath or near the voltage regulator. Partial metal vias are positioned between the signal traces and the voltage regulator. The partial metal vias extend from one trace layer of a circuit board towards another trace layer, but the partial metal vias do not connect the two trace layers. The partial metal vias partially shield the signal traces from noise caused by the voltage regulator.

公开(公告)号：US20210315097A1

公开(公告)日：2021-10-07

申请号：US17353163

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Roman Meltser ,  Prabhat Ranjan ,  Shivani R. Jain

IPC: H05K1/02

Abstract: In one embodiment, an apparatus includes a circuit board having a parallel bus with a first trace and a second trace, a first inductive coil coupled to the first trace, and a second inductive coil coupled to the second trace. The first and second inductive coils are arranged to inductively couple with one another to reduce cross talk effects in the parallel bus.

公开(公告)号：US20200373081A1

公开(公告)日：2020-11-26

申请号：US16989729

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Ranjul Balakrishnan ,  Sagar Dubey ,  Jackson Chung Peng Kong ,  Anil Baby

IPC: H01F27/36 ,  H01F27/24 ,  H01F27/02 ,  H01F41/00 ,  H05K1/18 ,  H05K1/02

Abstract: Embodiments of the present disclosure may relate to forming a metal shield around a molded ferrite inductor to reduce the electromagnetic energy radiated by the inductor during operation. The metal shield allows an inductor to be placed on a PCB with multiple signal routing layers below and close to the inductor, as well as micro strips on the surface of the PCB close to the inductor, to reliably route signals during operation. Other embodiments may be described and/or claimed.

公开(公告)号：US20180241113A1

公开(公告)日：2018-08-23

申请号：US15440983

申请日：2017-02-23

Applicant: Intel Corporation

Inventor： Arvind Sundaram ,  Ramaswamy Parthasarathy ,  Ranjul Balakrishnan ,  Vikas Mishra

IPC: H01P5/08 ,  H01R4/18 ,  H01P3/10 ,  H01P11/00 ,  H01P1/36 ,  H01R13/24 ,  H01Q1/38 ,  H01Q13/02 ,  H01Q1/48 ,  H01Q1/42

CPC classification number: H01P5/08 ,  H01P1/36 ,  H01P3/10 ,  H01P5/085 ,  H01P11/001 ,  H01Q1/38 ,  H01Q1/42 ,  H01Q1/48 ,  H01Q13/02 ,  H01Q13/26 ,  H01R4/18 ,  H01R13/24 ,  H01R13/6477 ,  H01R13/7193 ,  H01R43/24 ,  H05K1/183

Abstract: Embodiments of the present disclosure provide techniques and configurations for a cable assembly for single wire communications (SWC). In one instance, the cable assembly may comprise a wire having a wire end to couple with a signal launcher of an electronic device, and a first cover portion to house a first portion of the wire that extends from the wire end. The first cover portion may comprise a shape to conform to a shape of the signal launcher, and may be fabricated of a material with a dielectric constant above a threshold. The assembly may further comprise a second cover portion coupled with the first cover portion to house a second portion of the wire that extends from the first wire portion and protrudes from the first cover portion. The second cover portion may be fabricated of a ferrite material. Other embodiments may be described and/or claimed.

公开(公告)号：US10734393B2

公开(公告)日：2020-08-04

申请号：US16182972

申请日：2018-11-07

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Shanto A. Thomas ,  Ranjul Balakrishnan

IPC: H01L29/66 ,  H01L21/332 ,  H01L27/11512 ,  H01L27/108 ,  H01L25/065 ,  H01L23/00

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.

公开(公告)号：US20190109115A1

公开(公告)日：2019-04-11

申请号：US16210540

申请日：2018-12-05

Applicant: Intel Corporation

Inventor： Navneet K. Singh ,  Ranjul Balakrishnan

IPC: H01L25/065 ,  H01L23/498

Abstract: A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in electronic communication with at least one second microelectronic device through the microelectronic interposer which positions the at least one second microelectronic device outside a periphery of the first microelectronic device. The microelectronic interposer may further include at least one recess for achieving a desired height and/or enabling various configurations for the microelectronic package.