公开(公告)号：US20220091764A1

公开(公告)日：2022-03-24

申请号：US17540847

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Sreenivas MANDAVA ,  Jing LING

IPC: G06F3/06

Abstract: A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.

公开(公告)号：US20210264999A1

公开(公告)日：2021-08-26

申请号：US17315303

申请日：2021-05-08

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Bill NALE ,  Jongwon LEE ,  Sreenivas MANDAVA

IPC: G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C29/00

Abstract: A memory chip is described. The memory chip includes row hammer threat detection circuitry. The memory chip includes an output. The memory chip includes backpressure signal generation circuitry coupled between the row hammer detection circuitry and the output. The backpressure signal generation signal is to generate a backpressure signal to be sent from the output in response to detection by the row hammer threat detection circuitry of a row hammer threat.

公开(公告)号：US20180181336A1

公开(公告)日：2018-06-28

申请号：US15392912

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： John V. LOVELACE ,  Sreenivas MANDAVA ,  Debaleena DAS

IPC: G06F3/06

CPC classification number: G06F21/79 ,  G06F11/1048 ,  G06F2221/2143

Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

公开(公告)号：US20180004433A1

公开(公告)日：2018-01-04

申请号：US15684936

申请日：2017-08-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman GEETHA ,  Henk G. NEEFS ,  Brian S. MORRIS ,  Sreenivas MANDAVA ,  Massimo SUTERA

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20210382638A1

公开(公告)日：2021-12-09

申请号：US17411944

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Ronald ANDERSON ,  Lawrence D. BLANKENBECKLER ,  Pietro FRIGO ,  Jaemon FRANKO ,  Sreenivas MANDAVA

IPC: G06F3/06

Abstract: A memory system includes a memory device having a memory array that stores data based on address bits, including a row address. The memory system includes a memory controller having scrambler circuitry to apply a data mask to scramble data to be stored in the memory array. The scrambler can apply the data mask to scramble data for a write operation. The data scrambler can unscramble data for a read operation. The data mask has a pseudorandom pattern based at least in part on the row address of the data to be written or read.

公开(公告)号：US20220108764A1

公开(公告)日：2022-04-07

申请号：US17551499

申请日：2021-12-15

Applicant: Intel Corporation

Inventor： Jing LING ,  Sreenivas MANDAVA

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/18

Abstract: Adaptive Double Device Data Correction sparing uses memory addresses in increasing order. The last sparing address is stored as a memory address. Each system address for a processor memory transaction is converted to a memory address. The memory address is compared with the last sparing address to determine the Error Code Correction format for the processor memory transaction.

公开(公告)号：US20210382640A1

公开(公告)日：2021-12-09

申请号：US17411960

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Sreenivas MANDAVA ,  John V. LOVELACE

IPC: G06F3/06 ,  G06F11/10

Abstract: Initialization of a memory can have different phases, first initializing a portion of memory for BIOS (basic input/output system) and initializing other portions of memory while the BIOS is operating. The initialization of the memory can be performed by the error scrub engine. In a first mode of operation, the scrub engine can initialize memory locations, then transition to performing scrub operations.

公开(公告)号：US20210109577A1

公开(公告)日：2021-04-15

申请号：US17130686

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Sreenivas MANDAVA ,  Anders FOGH

IPC: G06F1/20 ,  G06F13/16 ,  G06F12/02

Abstract: A probabilistic scheme that uses temperature to reload an LFSR at runtime introduces randomness to prevent row hammer attacks. In one example, a memory controller includes input/output (I/O) interface circuitry to receive memory access requests from a processor. A linear feedback shift register (LFSR) in the memory controller is shifted in response to receipt of a memory access request to a target address. The shift register is compared a value in the LFSR with a pre-determined value. If the value in the LFSR is equal to the predetermined value, a refresh is triggered to one or more neighboring addresses of the target address. The LFSR is reloaded with one of multiple seeds based on a temperature (for example, from an on-die thermal sensor, a DIMM sensor, and/or other temperature). Selecting one of multiple seeds based on temperature on the fly makes the scheme unpredictable and robust against row hammer.