公开(公告)号：US20250112392A1

公开(公告)日：2025-04-03

申请号：US18980411

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Richard Canham ,  Ernesto Borboa Lizarraga ,  Daniel Neumann ,  Shelby Ferguson ,  Eric Buddrius ,  Hardikkumar Prajapati ,  Kirk Wheeler ,  Steven Klein ,  Shaun Immeker ,  Jeffory L. Smalley

IPC: H01R12/85

Abstract: A semiconductor package carrier used to support a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) as the semiconductor package is moved from a shipping tray to a land grid array (LGA) socket during assembly of an electronic device. The semiconductor package carrier including a carrier body including a plurality of support structures arranged to support a portion of the semiconductor package. The semiconductor package carrier further including a locking structure moveable between a first position and a second position, wherein the first position allows the support structures to receive the semiconductor package and the second position secures the semiconductor package to the carrier body. In some embodiments, the semiconductor package carrier may also include a thermal interface material (TIM) breaker to facilitate removal of a heatsink from the semiconductor package. Other embodiments are described and claimed.

公开(公告)号：US20220102892A1

公开(公告)日：2022-03-31

申请号：US17032587

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad ,  Joe Walczyk ,  Kuang Liu ,  Zhichao Zhang

IPC: H01R13/11 ,  H05K1/02 ,  H05K9/00

Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

公开(公告)号：US20220102883A1

公开(公告)日：2022-03-31

申请号：US17032595

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad

IPC: H01R12/71 ,  H01R43/26

Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.

公开(公告)号：US20250055217A1

公开(公告)日：2025-02-13

申请号：US18929426

申请日：2024-10-28

Applicant: Intel Corporation

Inventor： Min Pei ,  Lejie Liu ,  Ralph Miele ,  Phil Geng ,  Steven Klein

IPC: H01R13/24 ,  H01R12/71

Abstract: A Land Grid Array (LGA) interface assembly used to physically interface or connect a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) and a PCB, motherboard, etc. The LGA interface assembly including an LGA socket including a plurality of socket pins arranged and configured to contact a plurality of contact pads on the semiconductor package to enable data transfer. The socket pins including a multi-bend and/or zig-zag configuration arranged and configured to minimize lateral displacement of the socket pin relative to the contact pad during insertion of the semiconductor package into the LGA socket. Other embodiments are described and claimed.

公开(公告)号：US12009612B2

公开(公告)日：2024-06-11

申请号：US17032587

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad ,  Joe Walczyk ,  Kuang Liu ,  Zhichao Zhang

IPC: H01R13/11 ,  H05K1/02 ,  H05K9/00

CPC classification number: H01R13/11 ,  H05K1/0213 ,  H05K9/0022

Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

公开(公告)号：US20240222288A1

公开(公告)日：2024-07-04

申请号：US18090140

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： David Shia ,  Timothy Gosselin ,  Aravindha Antoniswamy ,  Sergio Antonio Chan Arguedas ,  Elah Bozorg-Grayeli ,  Johnny Cook, JR. ,  Steven Klein ,  Rick Canham

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/427 ,  H01L23/49

CPC classification number: H01L23/544 ,  H01L23/427 ,  H01L23/49 ,  H01L24/08 ,  H01L24/48 ,  H01L2224/08113 ,  H01L2224/48229 ,  H01L2924/15165 ,  H01L2924/1711 ,  H01L2924/173 ,  H01L2924/17724 ,  H01L2924/1776

Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.

公开(公告)号：US11916322B2

公开(公告)日：2024-02-27

申请号：US17032595

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad

IPC: H01R12/71 ,  H01R43/26

CPC classification number: H01R12/714 ,  H01R43/26

Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.

公开(公告)号：US20220069532A1

公开(公告)日：2022-03-03

申请号：US17008979

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： Feroz Mohammad ,  Steven Klein ,  Srikant Nekkanty

IPC: H01R33/76 ,  H01L23/498 ,  H01L23/32

Abstract: An integrated circuit assembly may be formed comprising an electronic socket having at least one conductive pin, wherein a portion of the conductive pin extends from the electronic socket. The integrated circuit assembly further comprises a conductive interposer including at least one conductive via having a conductive layer on a sidewall thereof. The conductive interposer is abutted against the electronic socket, such that the at least one conductive pin is inserted into the at least one conductive via and is biased against the conductive layer of the at least one conductive via. In further embodiments, an integrated circuit package may be electrically attached to the conductive interposer.