公开(公告)号：US12037434B2

公开(公告)日：2024-07-16

申请号：US17313932

申请日：2021-05-06

申请人： Intel Corporation

发明人： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

摘要： A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US11217455B2

公开(公告)日：2022-01-04

申请号：US16954419

申请日：2018-03-28

申请人： Intel Corporation

发明人： James M. Blackwell ,  Tayseer Mahdi

IPC分类号： H01L21/027 ,  H01L21/033 ,  C23C16/26 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

摘要： Carbon-based dielectric materials for semiconductor structure fabrication, and the resulting structures, are described. In an example, method of patterning a layer for a semiconductor structure includes forming a plurality of trenches in a dielectric layer above a semiconductor layer above a substrate to form a patterned dielectric layer. The method also includes filling the plurality of trenches with an adamantane-based carbon hardmask material. The method also includes removing the patterned dielectric layer selective to the adamantane-based carbon hardmask material. The method also includes using the adamantane-based carbon hardmask material to pattern the semiconductor layer.

公开(公告)号：US20240360264A1

公开(公告)日：2024-10-31

申请号：US18766426

申请日：2024-07-08

申请人： Intel Corporation

发明人： Eungnak Han ,  Gurpreet Singh ,  Tayseer Mahdi ,  Florian Gstrein ,  Lauren Doyle ,  Marie Krysak ,  James Blackwell ,  Robert Bristol

IPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/522 ,  H01L23/528

CPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

摘要： A chemical composition includes a polymer chain having a surface anchoring group at a terminus of the polymer chain. The surface anchoring group is metal or dielectric selective and the polymer chain further includes at least one of a photo-acid generator, quencher, or a catalyst. In some embodiments, the surface anchoring group is metal selective or dielectric selective. In some embodiments, the polymer chain includes side polymer chains where the side polymer chains include polymers of photo-acid generators, quencher, or catalyst.

公开(公告)号：US20200098629A1

公开(公告)日：2020-03-26

申请号：US16465526

申请日：2016-12-31

申请人： Intel Corporation

发明人： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC分类号： H01L21/768

摘要： In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US20220199462A1

公开(公告)日：2022-06-23

申请号：US17511693

申请日：2021-10-27

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Florian Gstrein ,  Eungnak Han ,  Marie Krysak ,  Tayseer Mahdi ,  Xuanxuan Chen ,  Brandon Jay Holybee

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

摘要： Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

公开(公告)号：US11024538B2

公开(公告)日：2021-06-01

申请号：US16465526

申请日：2016-12-31

申请人： Intel Corporation

发明人： Kevin L. Lin ,  Tayseer Mahdi ,  Jessica M. Torres ,  Jeffery D. Bielefeld ,  Marie Krysak ,  James M. Blackwell

IPC分类号： H01L21/768

摘要： In an example, there is disclosed an integrated circuit, having: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; and an etch-resistant plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect.

公开(公告)号：US12036578B1

公开(公告)日：2024-07-16

申请号：US16424338

申请日：2019-05-28

申请人： Intel Corporation

发明人： Florian Gstrein ,  James M. Blackwell ,  Eungnak Han ,  Rami Hourani ,  Tayseer Mahdi

IPC分类号： B05D3/00 ,  B01J19/00 ,  B05D3/10 ,  C07F9/28 ,  C07F9/38 ,  C07F9/40 ,  C25D11/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H05K1/18

CPC分类号： B05D3/002 ,  B01J19/006 ,  B05D3/10 ,  C07F9/28 ,  C07F9/38 ,  C07F9/40 ,  C07F9/4021 ,  C25D11/00 ,  H01L21/56 ,  H01L21/76831 ,  H01L23/293 ,  H01L23/5226 ,  H05K1/181 ,  H05K2201/0137 ,  H05K2201/0195

摘要： Embodiments herein describe techniques for a semiconductor device including an interconnect structure. The interconnect structure may have a segment of a passivant layer including a SAM. The SAM may include head groups, and chains attached to the head groups. The chains include functional groups that are cross-linkable at end or side of the chains to result in chain extension by reacting with another SAM or polymer, densification by crosslinking with an adjacent SAM, or polymerization having an initiator as the SAM or the SAM attached to another SAM. Other embodiments may be described and/or claimed.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

申请人： Intel Corporation

发明人： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC分类号： G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC分类号： C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

摘要： Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.

公开(公告)号：US20240113039A1

公开(公告)日：2024-04-04

申请号：US17957552

申请日：2022-09-30

申请人： Intel Corporation

发明人： Tayseer Mahdi ,  Grant Kloster ,  Florian Gstrein

IPC分类号： H01L23/00 ,  H01L21/02 ,  H01L23/29

CPC分类号： H01L23/562 ,  H01L21/02126 ,  H01L21/0217 ,  H01L23/291

摘要： Methods, device structures, and wafer treatment chemistries related to backside wafer treatments to reduce distortions and overlay errors due to wafer deformation during wafer chucking are described. A backside layer is applied to the wafer prior to chucking. The chemistry of the backside layer lowers the surface free energy of the wafer during chucking to eliminate or mitigate wafer deformation during wafer processing.

公开(公告)号：US20220199540A1

公开(公告)日：2022-06-23

申请号：US17125232

申请日：2020-12-17

申请人： Intel Corporation

发明人： Gurpreet Singh ,  Eungnak Han ,  Xuanxuan Chen ,  Tayseer Mahdi ,  Marie Krysak ,  Brandon Jay Holybee ,  Florian Gstrein

IPC分类号： H01L23/538

摘要： Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.