公开(公告)号：US5268590A

公开(公告)日：1993-12-07

申请号：US958583

申请日：1992-10-08

申请人： James R. Pfiester ,  Thomas C. Mele ,  Young Limb

发明人： James R. Pfiester ,  Thomas C. Mele ,  Young Limb

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L29/665 ,  H01L21/76885 ,  H01L21/8238 ,  H01L27/092 ,  Y10S257/915

摘要： A CMOS device and a method for its fabrication are disclosed. In one embodiment the CMOS device includes an NMOS transistor and a PMOS transistor each of which has silicided source and drain regions and a silicon gate electrode which includes a titanium nitride barrier layer. The NMOS transistor and PMOS transistors are coupled together by a silicon layer which is capped by a layer of titanium nitride barrier material. The source and drain regions are silicided with cobalt or other metal silicide which is prevented from reacting with the silicon gate electrode and interconnect by the presence of the titanium nitride barrier layer.

摘要翻译： 公开了一种CMOS器件及其制造方法。 在一个实施例中，CMOS器件包括NMOS晶体管和PMOS晶体管，每个NMOS晶体管和PMOS晶体管都具有硅化源极和漏极区域，以及包括氮化钛阻挡层的硅栅电极。 NMOS晶体管和PMOS晶体管通过由氮化钛屏障材料层覆盖的硅层耦合在一起。 源极和漏极区域被钴或其它金属硅化物硅化，其被防止与硅栅电极反应并且通过存在氮化钛阻挡层而互连。

公开(公告)号：US5352631A

公开(公告)日：1994-10-04

申请号：US991801

申请日：1992-12-16

申请人： Arkalgud R. Sitaram ,  James R. Pfiester

发明人： Arkalgud R. Sitaram ,  James R. Pfiester

IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/283

CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L21/2257 ,  H01L29/66545

摘要： A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

摘要翻译： 用于形成晶体管（10）的工艺通过提供衬底（12）开始。 场氧化物区域（14）或等效隔离形成在衬底（12）之上或之内。 形成栅极氧化物（16）和导电层（18）。 形成覆盖导电层（18）的掩模层（20）。 蚀刻掩模层（20）和导电层（18）以形成栅电极并限定漏区（19）和源极区（21）。 隔板（22）形成在栅电极附近。 在源极和漏极区（分别为21和19）上形成第一硅化区（26）。 掩模层防止栅电极硅化。 去除掩模层（20），并且形成覆盖栅电极的第二硅化区域（30）。 第二硅化物区域（30）和硅化物区域（26）由不同的硅化物制成。

公开(公告)号：US5319232A

公开(公告)日：1994-06-07

申请号：US76488

申请日：1993-06-14

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/225 ,  H01L21/331 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/10 ,  H01L29/72

CPC分类号： H01L29/66628 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/66287 ,  H01L29/66492 ,  H01L29/6653 ,  Y10S257/90

摘要： A transistor (10 or 11) and method of formation. The transistor (10) has a substrate (12). The substrate (12) has an overlying dielectric layer (14) and an insulated conductive control electrode (16) which overlies the dielectric layer (14). A dielectric region (18) overlies the insulated conductive control electrode (16), and a dielectric region (20) is adjacent to the insulated conductive control electrode (16). A spacer (30) is adjacent to the dielectric region (20). Epitaxial regions (24) are adjacent to the spacer (30) and the spacer (30) is overlying portions of the epitaxial regions (24). A dielectric region (26) overlies the epitaxial regions (24). Highly doped source and drain regions (32) underlie the epitaxial regions (24). LDD regions (28), which are underlying the spacer (30), are adjacent to and electrically connected to the source and drain regions (32).

摘要翻译： 一种晶体管（10或11）及其形成方法。 晶体管（10）具有基板（12）。 衬底（12）具有覆盖在电介质层（14）上的上覆电介质层（14）和绝缘导电控制电极（16）。 电介质区域（18）覆盖绝缘导电控制电极（16），电介质区域（20）与绝缘导电控制电极（16）相邻。 间隔物（30）与电介质区域（20）相邻。 外延区域（24）与间隔物（30）相邻，并且间隔物（30）覆盖外延区域（24）的部分。 电介质区域（26）覆盖在外延区域（24）上。 高掺杂源极和漏极区域（32）位于外延区域（24）的下面。 位于间隔物（30）下方的LDD区域（28）与源区和漏区（32）相邻并电连接。

公开(公告)号：US5166084A

公开(公告)日：1992-11-24

申请号：US753512

申请日：1991-09-03

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/306 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/6675 ,  H01L21/30604 ,  H01L29/66772 ,  H01L29/78648 ,  Y10S148/15

摘要： A process for fabricating an isolated silicon on insulator (SOI) field effect transistor (FET) (10, 11, 13, 15). The SOI FET is made on a substrate material (12). In one form, a first control electrode referred to as gate (24), is contained within the substrate (12) underlying a dielectric layer (14). A second control electrode referred to as gate (26) overlies a dielectric layer (28). A source and a drain current electrode are formed from a germanium-silicon layer (18). A silicon layer (16) forms an isolated channel region of the SOI FET. The gates (12, 24) are separated from the channel by gate dielectric layers (14, 28). The germanium-silicon layer (18) is much thicker than the silicon layer (16) which is made thin to provide a thin channel region. An optional nitride layer 20 overlies the germanium-silicon layer (18).

摘要翻译： 一种用于制造绝缘体上硅绝缘体（SOI）场效应晶体管（FET）（10,11,13,15）的工艺。 SOI FET在衬底材料（12）上制成。 在一种形式中，被称为栅极（24）的第一控制电极被包含在介电层（14）下面的衬底（12）内。 被称为栅极（26）的第二控制电极覆盖在电介质层（28）上。 源极和漏极电流电极由锗 - 硅层（18）形成。 硅层（16）形成SOI FET的隔离沟道区。 栅极（12,24）通过栅极电介质层（14,28）与沟道分离。 锗硅层（18）比制成薄以提供薄沟道区的硅层（16）厚得多。 可选的氮化物层20覆盖锗硅层（18）。

公开(公告)号：US5047812A

公开(公告)日：1991-09-10

申请号：US315668

申请日：1989-02-27

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7834 ,  H01L21/28132 ,  H01L29/4236

摘要： An insulated gate field effect device is disclosed having a channel region which includes both a horizontal and a vertical portion. The device is fabricated on a semiconductor substrate having a recess formed in its surface. The recess has a bottom forming a second surface with the wall of the recess extending between the first and second surfaces. A source region is formed at the first surface and a drain is formed at the second surface spaced apart from the wall. A channel region is defined along the wall and the second surface between the drain region and the source region. A gate insulator and gate electrode overlie the channel region.

摘要翻译： 公开了一种绝缘栅场效应器件，其具有包括水平和垂直部分的沟道区域。 该器件制造在具有在其表面上形成的凹部的半导体衬底上。 凹部具有形成第二表面的底部，凹部的壁在第一和第二表面之间延伸。 源区域形成在第一表面处，并且在与壁间隔开的第二表面处形成漏极。 沿着壁和漏极区域和源极区域之间的第二表面限定沟道区域。 栅极绝缘体和栅极电极覆盖沟道区域。

公开(公告)号：US5024959A

公开(公告)日：1991-06-18

申请号：US412059

申请日：1989-09-25

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823864 ,  H01L29/78 ,  H01L27/0928

摘要： An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region. The only lithography step needed in this portion of the process is one to protect the dopant source layer over the second region while sidewall spacers are being formed in the first region.

摘要翻译： 公开了一种使用减少数量的处理步骤的改进的LDD CMOS制造。 根据本发明的一个实施例，提供了具有相反导电类型的第一和第二表面区域的硅衬底。 第一和第二硅栅电极分别覆盖在第一和第二表面区域上。 包含第一导电类型的掺杂剂杂质的掺杂剂源层沉积在第一和第二栅电极上。 该掺杂剂源层被图案化以在第一硅栅电极的边缘处形成侧壁间隔物。 这些侧壁间隔物用于在形成于第一表面区域的器件上形成LDD结构。 在去除侧壁间隔物之后，加热结构以将掺杂剂杂质从掺杂剂源层扩散到第二表面区域中，以形成在该区域中形成的晶体管的源极和漏极区域。 在该方法的该部分中所需的唯一光刻步骤是在第二区域保护掺杂剂源层，同时在第一区域中形成侧壁间隔物的步骤。

公开(公告)号：US4978626A

公开(公告)日：1990-12-18

申请号：US240013

申请日：1988-09-02

申请人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

发明人： Stephen S. Poon ,  James R. Pfiester ,  Frank K. Baker ,  Jeffrey L. Klein

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L21/823828 ,  H01L29/78 ,  H01L29/7836 ,  H01L27/0928

摘要： An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step. In other forms, an inverse-T gate structure LDD transistor is formed, and an LDD transistor is formed via a process having a reduced number of ion implants steps.

摘要翻译： 通过使用确保栅极氧化物层不会被无意蚀刻而不被静电电荷破裂的工艺形成LDD晶体管。 在半导体衬底之上的栅极氧化物层上形成具有不同掺杂水平的至少两个厚度的栅电极材料。 使用化学蚀刻，其中通过监测化学蚀刻反应的化学产品和化学反应物的比例，可以容易地检测到栅电极材料的蚀刻中的特定端点。 在离子注入期间允许一小层栅电极材料保留在栅极氧化物层上方，并且在制造LDD晶体管时形成和去除栅极侧壁间隔物。 在形成大多数LDD晶体管之后，去除栅电极材料的剩余保护厚度，暴露的栅极氧化层暴露于最后的氧化退火步骤。 在其他形式中，形成逆T栅极结构LDD晶体管，并且通过具有减少数量的离子注入步骤的工艺形成LDD晶体管。

公开(公告)号：US4876213A

公开(公告)日：1989-10-24

申请号：US264925

申请日：1988-10-31

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/76895 ,  H01L21/823835 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L27/0928 ,  Y10S257/90

摘要： A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant and the silicide formation facilitates the closer spacing of the silicide region to the gate edge. Prior to the salicidation, a silicon overetch is performed to remove the P+ implant in the source/drain and poly regions of the NMOST. The silicon overetch forms a concave surface on the N+ source/drain regions, which allows salicide formation closer to the edge of the channel. Due to the proximity of the edge of the silicide to the edge of the channel, the series resistance of the NMOST is significantly reduced.

摘要翻译： 一种使用用于源极/漏极注入和自对准硅化物形成的一个侧壁间隔物来制造CMOS器件的方法，从而提供改进的水平源极/漏极结构。 用于源/漏注入和硅化物形成两者的一个侧壁间隔件有助于硅化物区域与栅极边缘更近的间隔。 在水解之前，执行硅过蚀刻以去除NMOST的源极/漏极和多晶区域中的P +注入。 硅过蚀刻在N +源极/漏极区域上形成凹面，这使得自对准硅化物更靠近沟道边缘。 由于硅化物边缘与沟道边缘的接近，NMOST的串联电阻显着降低。

公开(公告)号：US4847213A

公开(公告)日：1989-07-11

申请号：US242654

申请日：1988-09-12

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L21/762 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/76218 ,  H01L21/76213 ,  H01L21/823878 ,  H01L27/0928 ,  Y10S438/981

摘要： A process is disclosed for the selective oxidation of MOS devices which preferentially removes implanted field doping from selected silicon substrate regions. In one embodiment, a CMOS substrate is provided with an overlying layer of silicon oxide and a layer of polycrystalline silicon. Active and field regions are defined in each of the CMOS device regions. A blanket boron implantation dopes both the N-type and P-type field regions. The N-type field region is selectively oxidized at a greater oxidation rate than is the P-type field region to cause a greater segregation of boron impurities into the growing oxide over the N-type field region. Regions of enhanced boron doping are thus formed under the field oxide in the P-type region, but not in the N-type region.

摘要翻译： 公开了用于选择性氧化MOS器件的工艺，其优先地从选择的硅衬底区域去除注入的场掺杂。 在一个实施例中，CMOS衬底设置有氧化硅的上层和多晶硅层。 在每个CMOS器件区域中定义有源和场区域。 覆盖硼注入掺杂了N型和P型场区。 N型场区以比P型场区更高的氧化速率被选择性地氧化，从而在N型场区域上产生更大的硼杂质偏析到生长的氧化物中。 因此，在P型区域的场氧化物下形成增强的硼掺杂区域，但不形成在N型区域中。

公开(公告)号：US4714519A

公开(公告)日：1987-12-22

申请号：US31304

申请日：1987-03-30

申请人： James R. Pfiester

发明人： James R. Pfiester

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L21/306 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L29/66575 ,  H01L21/2255 ,  H01L21/28105 ,  H01L29/4983

摘要： A process for forming an insulated gate field effect transistor (IGFET) having a semiconductor gate with a central portion and end portions on either side thereof where the portions are of two different conductivity types. Typically, a central portion of the gate, such as a doped polysilicon portion of a first conductivity type, is flanked by end portions near the source/drain regions, where the end portions are doped with an impurity of a second conductivity type. The central portion of the gate is formed by conventional gate patterning whereas the end portions are formed by typical procedures for forming sidewall spacers using a conformal layer of in situ doped polycrystalline silicon (polysilicon) or other semiconductor material and an anisotropic etch.

摘要翻译： 一种用于形成绝缘栅场效应晶体管（IGFET）的工艺，该绝缘栅场效应晶体管（IGFET）具有半导体栅极，该半导体栅极具有中心部分，其两侧的端部具有两种不同导电类型。 通常，栅极的中心部分，例如第一导电类型的掺杂多晶硅部分，其侧面是靠近源极/漏极区域的端部，其中末端部分掺杂有第二导电类型的杂质。 栅极的中心部分通过常规栅极图案形成，而端部通过使用原位掺杂多晶硅（多晶硅）或其它半导体材料的共形层和各向异性蚀刻形成侧壁间隔物的典型步骤形成。