公开(公告)号：US08476692B2

公开(公告)日：2013-07-02

申请号：US13037502

申请日：2011-03-01

申请人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/778

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20110215392A1

公开(公告)日：2011-09-08

申请号：US13037502

申请日：2011-03-01

申请人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  WoonKyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L23/48 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20150145018A1

公开(公告)日：2015-05-28

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20150348982A1

公开(公告)日：2015-12-03

申请号：US14819841

申请日：2015-08-06

申请人： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

发明人： Jeeyong Kim ,  Woonkyung LEE ,  Sunggil KIM ,  Jin-Kyu KANG ,  Jung-Hwan LEE ,  Bonyoung KOO ,  Kihyun HWANG ,  Byoungsun JU ,  Jintae NOH

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L23/535

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US09443863B2

公开(公告)日：2016-09-13

申请号：US14819841

申请日：2015-08-06

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L27/115 ,  H01L23/535 ,  H01L29/78 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

公开(公告)号：US09129950B2

公开(公告)日：2015-09-08

申请号：US14568737

申请日：2014-12-12

申请人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

发明人： Jeeyong Kim ,  Woonkyung Lee ,  Sunggil Kim ,  Jin-Kyu Kang ,  Jung-Hwan Lee ,  Bonyoung Koo ,  Kihyun Hwang ,  Byoungsun Ju ,  Jintae Noh

IPC分类号： H01L29/49 ,  H01L21/28 ,  H01L23/48 ,  H01L29/788 ,  H01L29/792 ,  H01L21/768 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/28 ,  H01L21/76841 ,  H01L23/48 ,  H01L23/535 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4958 ,  H01L29/78 ,  H01L29/788 ,  H01L29/7883 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a charge storage pattern formed on a substrate; a dielectric pattern formed on the charge storage pattern; a first conductive pattern including silicon doped with a first impurity of a first concentration, the first conductive pattern being disposed on the dielectric pattern; and a second conductive pattern including metal silicide doped with a second impurity of a second concentration, the second conductive pattern being disposed on the first conductive pattern. The first concentration may be higher than the second concentration.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括形成在衬底上的电荷存储图案; 形成在电荷存储图案上的电介质图案; 第一导电图案，包括掺杂有第一浓度的第一杂质的硅，所述第一导电图案设置在所述电介质图案上; 以及第二导电图案，其包括掺杂有第二浓度的第二杂质的金属硅化物，所述第二导电图案设置在所述第一导电图案上。 第一浓度可能高于第二浓度。

公开(公告)号：US20120181693A1

公开(公告)日：2012-07-19

申请号：US13241741

申请日：2011-09-23

申请人： Jeeyong Kim ,  Jong-Hyun Park ,  Jin-Kyu Kang ,  Joonhee Lee

发明人： Jeeyong Kim ,  Jong-Hyun Park ,  Jin-Kyu Kang ,  Joonhee Lee

IPC分类号： H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/76834 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53285 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device may include an upper interconnection on a substrate and an anti-reflection pattern disposed on the upper interconnection. The anti-reflection pattern may include a compound including a metal, carbon and nitrogen.

摘要翻译： 半导体器件可以包括在衬底上的上互连和设置在上互连上的抗反射图案。 抗反射图案可以包括包含金属，碳和氮的化合物。

公开(公告)号：US09666525B2

公开(公告)日：2017-05-30

申请号：US15201994

申请日：2016-07-05

申请人： Jeeyong Kim ,  Daeseok Byeon ,  Jung-Hwan Lee ,  Sanghoon Ahn

发明人： Jeeyong Kim ,  Daeseok Byeon ,  Jung-Hwan Lee ,  Sanghoon Ahn

IPC分类号： H01L29/792 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11573

CPC分类号： H01L23/5226 ,  H01L21/7682 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2221/1047

摘要： Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.