公开(公告)号：US20130320550A1

公开(公告)日：2013-12-05

申请号：US13607012

申请日：2012-09-07

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10885

Abstract: A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming multiple layers of spacer layers with a capping layer interposed therebetween over the bit line structures, exposing a surface of the substrate by selectively etching the spacer layers, forming air gaps and capping spacers for covering upper portions of the air gaps by selectively etching the capping layer, and forming storage node contact plugs between the bit line structures.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成多个位线结构，在位线结构之间形成多层间隔层，其中封盖层介于其间，通过选择性地蚀刻间隔层而露出衬底的表面， 通过选择性地蚀刻覆盖层形成气隙和封盖间隔物，以覆盖气隙的上部，以及在位线结构之间形成储存节点接触塞。

公开(公告)号：US20120009760A1

公开(公告)日：2012-01-12

申请号：US13012313

申请日：2011-01-24

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L29/7827 ,  H01L21/2257 ,  H01L21/32 ,  H01L21/32134 ,  H01L21/32139 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/66666

Abstract: A method for fabricating an etching barrier includes forming wall bodies with a trench in between the wall bodies in a semiconductor substrate. An etching barrier is formed by performing a deposition having a directionality in an oblique direction with respect to the surface of the semiconductor substrate, wherein one of two bottom edge portions of the trench is not covered by the deposition due to a shadow effect by upper portions of the wall bodies.

Abstract translation: 蚀刻阻挡层的制造方法包括在半导体基板的壁体之间形成具有沟槽的壁体。 通过执行相对于半导体衬底的表面具有倾斜方向的定向性的沉积形成蚀刻阻挡层，其中沟槽的两个底部边缘部分之一不被沉积覆盖，这是由于上部的阴影效应 的墙体。

公开(公告)号：US20090111238A1

公开(公告)日：2009-04-30

申请号：US12118264

申请日：2008-05-09

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L29/78 ,  H01L29/7846

Abstract: A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.

Abstract translation: 通过在具有PMOS区域的半导体衬底中限定沟槽，能够选择性地施加不同应力以提高PMOS晶体管的电流驱动能力的半导体器件; 在沟槽的侧壁上选择性地形成缓冲层; 形成绝缘层以填充沟槽; 退火半导体衬底，使得通过氧化缓冲层在PMOS晶体管的沟道长度方向施加压应力; 去除绝缘层的部分，从而形成隔离层; 以及在半导体衬底的PMOS区上形成PMOS晶体管。

公开(公告)号：US20120205779A1

公开(公告)日：2012-08-16

申请号：US13337481

申请日：2011-12-27

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/60 ,  H01L21/30625 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided.

Abstract translation: 提供制造半导体器件的方法。 该方法包括在单元区域和周边区域中形成第一模具层，形成穿过单元区域中的第一模具层的第一存储节点和在周边区域中贯穿第一模具层的第一触点，形成第二模具 形成在第一模具层上的第二存储节点，形成穿过第二模具层的第二存储节点，以连接到第一存储节点中的相应的第一存储节点，将单元区域中的第二模具层和单元区域中的第一模具层移除到 离开第一模具层在周边区域，并形成穿过第一层间绝缘层以连接到第一触点的第二触点。 还提供了相关设备。

公开(公告)号：US20090267180A1

公开(公告)日：2009-10-29

申请号：US12245318

申请日：2008-10-03

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device that has a reduced fuse thickness without compromising the bondability of an associated pad and a method for manufacturing the same is described. The semiconductor device includes a pad and a fuse formed on a planar level. The pad and fuse are formed using a metal according to the metal used for the planar level on which the pad and fuse are formed. The pad is formed such that the center portion of the pad is positioned lower than that of the fuse. During the opening of the pad, the thickness of the fuse is reduced without reducing the thickness of the pad. A subsequent repair process can then be easily performed on the fuse having the reduced thickness without degrading the bondability of the pad.

Abstract translation: 描述了具有减小的熔丝厚度而不损害相关焊盘的可焊接性的半导体器件及其制造方法。 半导体器件包括形成在平面级上的焊盘和熔丝。 焊盘和熔丝使用根据用于形成焊盘和熔丝的平面级的金属的金属形成。 焊盘形成为使得焊盘的中心部分定位成低于保险丝的中心部分。 在焊盘打开期间，熔丝的厚度减小而不减小焊盘的厚度。 然后可以容易地对具有减小的厚度的熔丝执行随后的修复过程，而不降低焊盘的可焊接性。

公开(公告)号：US20120135573A1

公开(公告)日：2012-05-31

申请号：US13160689

申请日：2011-06-15

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/2257 ,  H01L27/10873 ,  H01L27/10885 ,  H01L29/41741 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for manufacturing a vertical transistor having a one side contact includes: forming separate active regions using trenches, on a semiconductor substrate, the active regions having first and second side surfaces facing the trenches; forming a first liner on the first and second side surfaces; forming a second liner which exposes a lower portion of the first liner on the first side surface; forming a third liner covering the portion of the first layer exposed by the second liner; forming a sacrifice layer on the third liner to fill the trench; forming an etch barrier to selectively expose upper end portions of the first to third liners positioned adjacent to the first side surface; selectively removing the third liner not covered by the etch barrier to expose a portion of the first liner not covered by the second liner; selectively removing the exposed portion of the first liner to expose a lower portion of the first side surface; and forming a buried bit line contacted with the exposed portion of the first side surface.

Abstract translation: 一种用于制造具有一侧触点的垂直晶体管的方法包括：在半导体衬底上形成具有沟槽的分离的有源区，所述有源区具有面向沟槽的第一和第二侧表面; 在所述第一和第二侧表面上形成第一衬垫; 形成在所述第一侧表面上暴露所述第一衬垫的下部的第二衬垫; 形成覆盖由第二衬套暴露的第一层的部分的第三衬垫; 在第三衬垫上形成牺牲层以填充沟槽; 形成蚀刻阻挡层以选择性地暴露位于邻近第一侧表面的第一至第三衬垫的上端部分; 选择性地移除未被蚀刻阻挡层覆盖的第三衬垫，以暴露未被第二衬垫覆盖的第一衬垫的一部分; 选择性地去除所述第一衬里的暴露部分以暴露所述第一侧表面的下部; 以及形成与所述第一侧表面的暴露部分接触的掩埋位线。

公开(公告)号：US20170148678A1

公开(公告)日：2017-05-25

申请号：US15423602

申请日：2017-02-03

Applicant: Sehoon Yoo ,  Chang Woo LEE ,  Jun Ki KIM ,  Jeong Han KIM ,  Young Ki KO

Inventor： Sehoon Yoo ,  Chang Woo LEE ,  Jun Ki KIM ,  Jeong Han KIM ,  Young Ki KO

IPC: H01L21/768 ,  B23K1/00 ,  B23K3/06 ,  H01L23/48

CPC classification number: H01L21/76898 ,  B23K1/0016 ,  B23K1/20 ,  B23K3/06 ,  B23K3/0646 ,  B23K3/087 ,  B23K2101/40 ,  H01L23/481

Abstract: A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air outlet for exhausting air from the accommodation space; a fixing unit for fixing the wafer having a via formed in one surface in the accommodation space to seal the accommodation space airtight; and a pressing unit for pressing a bottom of the molten solder arranged in the solder bath and moving the molten solder upward, to fill the molten solder in the via.

公开(公告)号：US20120007171A1

公开(公告)日：2012-01-12

申请号：US13077116

申请日：2011-03-31

Applicant: Baek Mann KIM ,  Jun Ki KIM ,  Yong Seok EUN ,  Kyong Bong ROUH

Inventor： Baek Mann KIM ,  Jun Ki KIM ,  Yong Seok EUN ,  Kyong Bong ROUH

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/10876 ,  H01L21/2257 ,  H01L27/10888 ,  H01L29/456 ,  H01L29/66666 ,  H01L29/7827

Abstract: A semiconductor memory device includes an active region protruding upward from a substrate, wherein the active region is arranged next to a trench on the substrate, a first impurity region formed at an upper portion of the active region, a second impurity region formed at a lower portion of the active region, a gate dielectric layer formed along a side of the active region between the first impurity region and the second impurity region, a gate electrode layer formed on the gate dielectric layer, a buried bit line formed at a lower portion of the trench, and a polysilicon layer formed over the buried bit line, wherein the polysilicon layer electrically connects the buried bit line with the second impurity region.

Abstract translation: 半导体存储器件包括从衬底向上突出的有源区，其中有源区布置在衬底上的沟槽旁边，形成在有源区的上部的第一杂质区，形成在下部的第二杂质区 有源区的一部分，沿着第一杂质区和第二杂质区之间的有源区的一侧形成的栅介质层，形成在栅介质层上的栅电极层，形成在栅电介质层的下部的掩埋位线 所述沟槽和形成在所述掩埋位线上的多晶硅层，其中所述多晶硅层将所述掩埋位线与所述第二杂质区电连接。

公开(公告)号：US20100323495A1

公开(公告)日：2010-12-23

申请号：US12861111

申请日：2010-08-23

Applicant: Jun Ki KIM ,  Soo Hyun KIM ,  Hyun Chul SOHN ,  Se Aug JANG

Inventor： Jun Ki KIM ,  Soo Hyun KIM ,  Hyun Chul SOHN ,  Se Aug JANG

IPC: H01L21/762 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7853

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Abstract translation: 公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。 该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层 去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域， 对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

公开(公告)号：US20100167538A1

公开(公告)日：2010-07-01

申请号：US12470069

申请日：2009-05-21

Applicant: Jun Ki KIM

Inventor： Jun Ki KIM

IPC: H01L21/768

CPC classification number: H01L21/02063

Abstract: A method for removing native oxide that remains on a surface of a semiconductor device is presented. The manufacturing method includes the steps of placing, supplying, moving, and annealing. The placing step includes placing a semiconductor substrate into a first process chamber. The supplying step includes supplying an etchant gas that reacts with the native oxide when the first process chamber is purged and sealed away from air. The moving step includes moving the semiconductor substrate with the byproduct formed on it into a second process chamber in which the moving step can be exposed to air. The annealing the semiconductor substrate in the second process chamber removes the byproduct.

Abstract translation: 提出了一种去除残留在半导体器件表面上的自然氧化物的方法。 该制造方法包括放置，供给，移动和退火的步骤。 放置步骤包括将半导体衬底放置在第一处理室中。 供应步骤包括当第一处理室被吹扫并且与空气密封时，提供与天然氧化物反应的蚀刻剂气体。 移动步骤包括将形成在其上的副产品的半导体衬底移动到第二处理室中，其中移动步骤可以暴露于空气中。 在第二处理室中退火半导体衬底去除副产物。