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96 条记录 (耗时 0.034 秒)

    Technique to suppress bitline leakage current
    6.
    发明授权
    Technique to suppress bitline leakage current 有权
    抑制位线漏电流的技术

    公开(公告)号：US07414896B2

    公开(公告)日：2008-08-19

    申请号：US11225465

    申请日：2005-09-13

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G11C7/10

    CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C2207/2227

    摘要： Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.

    摘要翻译： 提供了可以帮助减少存储器件中的待机电流的方法和装置。 通过将均衡和预充电功能分离成单独的电路结构，可以消除预充电电压源和有缺陷字线之间的电流路径（例如，由于制造缺陷而对位线的无意的短路）。

    Technique to suppress leakage current
    7.
    发明授权
    Technique to suppress leakage current 有权
    抑制漏电流的技术

    公开(公告)号：US07397708B2

    公开(公告)日：2008-07-08

    申请号：US11196369

    申请日：2005-08-03

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G11C7/10

    CPC分类号： G11C11/4085 ,  G11C8/08

    摘要： Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operational mode and the wordline is driven to a downward-driven low voltage if the wordline driver is in a standby mode. The driver transistor is electrically isolated from the downward-driven low voltage of the wordline when the wordline driver is in the standby mode. A leakage current in the wordline driver is thereby reduced.

    摘要翻译： 本发明的实施例通常提供具有减小的漏电流的方法和字线驱动器。 在一个实施例中，如果字线驱动器处于操作模式，则字线驱动器的驱动器晶体管将字线驱动到升压高电压，并且如果字线驱动器处于待机状态，则字线被驱动到向下驱动的低电压 模式。 当字线驱动器处于待机模式时，驱动晶体管与字线的向下驱动的低电压电隔离。 因此，字线驱动器中的漏电流减小。

    ERROR CORRECTION IN MEMORY DEVICES
    8.
    发明申请
    ERROR CORRECTION IN MEMORY DEVICES 有权
    存储器件中的错误校正

    公开(公告)号：US20080133994A1

    公开(公告)日：2008-06-05

    申请号：US11566774

    申请日：2006-12-05

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1008

    摘要： Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.

    摘要翻译： 本发明的实施例总体上提供了一种用于校正存储器件中的错误的方法和装置。 在一个实施例中，该方法包括接收读取命令的读取命令和读取命令的读取地址以及从对应于读取地址的存储器件的第一位置读取数据。 该方法还包括读取对应于读取地址的纠错信息。 如果错误校正信息指示数据中的错误，则校正数据中的错误以产生校正数据，并且从存储器件输出校正数据。 校正的数据也被写回存储器件中对应于读取地址的第二位置。

    Twin-cell bit line sensing configuration
    9.
    发明授权
    Twin-cell bit line sensing configuration 失效
    双电池位线检测配置

    公开(公告)号：US07177216B2

    公开(公告)日：2007-02-13

    申请号：US10992826

    申请日：2004-11-19

    申请人： Jungwon Suh ,  Jong-Hoon Oh

    发明人： Jungwon Suh ,  Jong-Hoon Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C2211/4013

    摘要： Twin-cell bit line sensing structures and techniques are provided. Utilizing a folded bit line like structure, with bit line and complementary bit lines located together, sense amplifiers can be between cell arrays. Bit line switches, responsive to activated word lines in an array, may be used to selectively couple bit line pairs of the shared arrays with the sense amplifiers with a single word line activation.

    摘要翻译： 提供双电池位线感测结构和技术。 利用折叠的位线结构，位线和互补位线位于一起，感测放大器可以在单元阵列之间。 响应于阵列中激活的字线的位线开关可用于通过单个字线激活来选择性地将共享阵列的位线对与感测放大器耦合。

    Multichip package with clock frequency adjustment
    10.
    发明申请
    Multichip package with clock frequency adjustment 有权

    公开(公告)号：US20060155503A1

    公开(公告)日：2006-07-13

    申请号：US11370559

    申请日：2006-03-08

    申请人： Jong-Hoon Oh

    发明人： Jong-Hoon Oh

    IPC分类号： G01K1/08 ,  G06F15/00

    CPC分类号： G06F1/206

    摘要： One embodiment of the present invention provides a multi-chip package including a logic device providing a clock signal having a frequency and a memory device. The memory device receives the clock signal and operates at the clock signal frequency. The memory device includes a temperature sensor providing a temperature signal indicative of a temperature of the memory device, wherein the logic device adjusts the clock signal frequency bases on the temperature signal.