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公开(公告)号：US11948646B2
公开(公告)日：2024-04-02
申请号：US18305654
申请日：2023-04-24
Applicant: Kioxia Corporation
Inventor： Kosuke Yanagidaira , Mario Sako
CPC classification number: G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through tis second and third transistors.
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公开(公告)号：US11862248B2
公开(公告)日：2024-01-02
申请号：US18161274
申请日：2023-01-30
Applicant: Kioxia Corporation
Inventor： Mai Shimizu , Koji Kato , Yoshihiko Kamata , Mario Sako
CPC classification number: G11C16/08 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US11501825B2
公开(公告)日：2022-11-15
申请号：US17349106
申请日：2021-06-16
Applicant: Kioxia Corporation
Inventor： Mario Sako
IPC: G11C16/06 , G11C11/4091 , G11C11/4094 , G11C5/06 , G11C11/4096 , G11C11/4076 , G11C11/4074
Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a bit line, and a sense amplifier. The sense amplifier includes: a first node configured to be electrically coupled to the bit line; a first transistor in which a gate is coupled to the first node, and which is configured to be coupled to a second node; a second transistor configured to couple the second node and a third node; and a third transistor in which a gate is coupled to the third node, and which is configured to be coupled to the first node. The sense amplifier applies a second voltage obtained by amplifying a first voltage of the first node to the third node, and applies a third voltage obtained by amplifying the second voltage to the first node.
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公开(公告)号：US11417401B2
公开(公告)日：2022-08-16
申请号：US17008209
申请日：2020-08-31
Applicant: KIOXIA CORPORATION
Inventor： Mario Sako , Hiromitsu Komai , Masahiro Yoshihara
IPC: G11C16/26 , H01L23/522 , G11C16/04 , G11C16/10 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L27/11556
Abstract: A semiconductor memory device includes a bit line, a first memory cell electrically connected to the bit line, and a sense amplifier connected to the bit lin. The sense amplifier includes a first capacitor element having an electrode that is connected to a first node electrically connectable to the bit line, a first transistor having a gate connected to the first node and a first end connectable to a second node, a second transistor having a first end connected to the second node and a second end connected to a third node, a second capacitor element having an electrode connected to the third node, and a latch circuit connected to the second node.
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公开(公告)号：US20220157380A1
公开(公告)日：2022-05-19
申请号：US17591216
申请日：2022-02-02
Applicant: KIOXIA CORPORATION
Inventor： Mai Shimizu , Koji Kato , Yoshihiko Kamata , Mario Sako
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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Patent Agency Ranking
公开(公告)号：US11127470B2
公开(公告)日：2021-09-21
申请号：US16902145
申请日：2020-06-15
Applicant: KIOXIA CORPORATION
Inventor： Mario Sako
Abstract: According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell electrically coupled to the first bit line; and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.
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公开(公告)号：US11670383B2
公开(公告)日：2023-06-06
申请号：US17575554
申请日：2022-01-13
Applicant: KIOXIA CORPORATION
Inventor： Kosuke Yanagidaira , Mario Sako
CPC classification number: G11C16/26 , G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/30
Abstract: A semiconductor memory includes memory cells, a word line and bit lines of the memory cells, sense amplifiers connected to the bit lines, respectively, and a controller. Each sense amplifier includes first, second, and third transistors. The third transistor has one end connected to each of the first and second transistors, and the other end connected to a corresponding bit line. During a read operation, at a first time of a first period during which the controller applies a first read voltage to the word line, the controller applies a first voltage higher than ground voltage to the first transistor, and a second voltage to the second transistor. Also, at the first time, a first sense amplifier applies a voltage to a first bit line through its first and third transistors, and a second sense amplifier applies a voltage to a second bit line through the second and third transistors.
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公开(公告)号：US11568939B2
公开(公告)日：2023-01-31
申请号：US17183805
申请日：2021-02-24
Applicant: KIOXIA CORPORATION
Inventor： Mario Sako
Abstract: A semiconductor storage device includes a bit line, a memory cell transistor electrically connected to the bit line, and a sense amplifier that reads data from the memory cell transistor via the bit line. During an operation of determining first data and second data, while continuously applying a first voltage to a gate of the memory cell transistor, the sense amplifier first determines the first data based upon a second voltage, and then determines the second data based upon a third voltage lower than the second voltage.
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公开(公告)号：US12106808B2
公开(公告)日：2024-10-01
申请号：US18485630
申请日：2023-10-12
Applicant: Kioxia Corporation
Inventor： Mai Shimizu , Koji Kato , Yoshihiko Kamata , Mario Sako
CPC classification number: G11C16/08 , G11C11/5642 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US11600328B2
公开(公告)日：2023-03-07
申请号：US17591216
申请日：2022-02-02
Applicant: KIOXIA CORPORATION
Inventor： Mai Shimizu , Koji Kato , Yoshihiko Kamata , Mario Sako
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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