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    Semiconductor memory cells with shared p-type well
    1.
    发明授权
    Semiconductor memory cells with shared p-type well 有权
    具有共享p型的半导体存储器单元

    公开(公告)号：US07710764B2

    公开(公告)日：2010-05-04

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C11/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit includes: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    Semiconductor integrated circuit with memory redundancy circuit
    2.
    发明申请
    Semiconductor integrated circuit with memory redundancy circuit 有权

    公开(公告)号：US20070286001A1

    公开(公告)日：2007-12-13

    申请号：US11783123

    申请日：2007-04-06

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    Semiconductor integrated circuit with memory redundancy circuit
    3.
    发明授权
    Semiconductor integrated circuit with memory redundancy circuit 有权
    半导体集成电路与存储器冗余电路

    公开(公告)号：US07219272B2

    公开(公告)日：2007-05-15

    申请号：US10170583

    申请日：2002-06-14

    申请人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    发明人： Kenichi Osada ,  Koichiro Ishibashi ,  Yoshikazu Saitou ,  Masashige Harada ,  Takehiko Kijima

    IPC分类号： G11C29/00 ,  G06F11/00 ,  G11C7/00

    CPC分类号： G06F11/1008 ,  G11C29/848

    摘要： A semiconductor integrated circuit with memory redundancy circuit to address the problems of increased area, power consumption and access time which is caused by using an ECC circuit for error correction. The circuit comprises: a plurality of memory mats; a local bus, parallel to word lines, which transfers read data and write data from memory cells; a global bus for writing, parallel to data lines, which transfers write data from an input pad IO; a global bus for reading, parallel to data lines, which transfers read data to an output pad IO; and at least one error correction circuit located at an intersection of the global buses and the local bus. Reading and writing may each be completed in a single cycle, and during a write operation, data which is different from data previously read is written. By this configuration, an increase in area and power consumption can be avoided and errors such as soft errors can be corrected.

    摘要翻译： 一种具有存储器冗余电路的半导体集成电路，用于解决由使用ECC电路进行纠错引起的增加的面积，功耗和访问时间的问题。 该电路包括：多个存储垫; 平行于字线的本地总线，其传送读取数据并从存储器单元写入数据; 与数据线并行的写入全局总线，其从输入焊盘IO传送写入数据; 用于读取数据线的全局总线，其将读取的数据传送到输出焊盘IO; 以及位于全局总线和本地总线的交叉点处的至少一个纠错电路。 读取和写入可以在单个周期中完成，并且在写入操作期间，写入与先前读取的数据不同的数据。 通过这种配置，可以避免面积和功耗的增加，并且可以校正诸如软错误的错误。

    Logic circuit and semiconductor device
    4.
    发明授权
    Logic circuit and semiconductor device 有权
    逻辑电路和半导体器件

    公开(公告)号：US06756814B2

    公开(公告)日：2004-06-29

    申请号：US10345242

    申请日：2003-01-16

    申请人： Yoshikazu Saitou ,  Kenichi Osada

    发明人： Yoshikazu Saitou ,  Kenichi Osada

    IPC分类号： H03K19175

    CPC分类号： H03K19/0016

    摘要： The present invention is directed to simplify a circuit for fixing an output logic of a logic gate while suppressing a subthreshold current. A logic circuit has an n-channel type first transistor capable of interrupting power supply to a logic gate in accordance with an input control signal, and a p-channel type second transistor capable of fixing an output node of the logic gate to a high level interlockingly with the power supply interrupting operation by the first transistor, and a threshold of the first transistor is set to be higher than that of a transistor as a component of the logic gate. Means for interrupting the power supply to the logic gate is realized by the first transistor, and means for fixing an output node of the logic gate to the high level is realized by the second transistor, thereby simplifying the circuit for fixing the output logic of the logic gate while suppressing a subthreshold current.

    摘要翻译： 本发明旨在简化用于在抑制亚阈值电流的同时固定逻辑门的输出逻辑的电路。 逻辑电路具有能够根据输入控制信号中断到逻辑门的电源的n沟道型第一晶体管，以及能够将逻辑门的输出节点固定为高电平的p沟道型第二晶体管 与第一晶体管的电源中断操作互锁，并且将第一晶体管的阈值设置为高于作为逻辑门的组件的晶体管的阈值。 用于中断对逻辑门的电源的装置由第一晶体管实现，并且通过第二晶体管实现将逻辑门的输出节点固定为高电平的装置，从而简化用于固定逻辑门的输出逻辑的电路 同时抑制亚阈值电流。