公开(公告)号：US20240090239A1

公开(公告)日：2024-03-14

申请号：US18176557

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Kiichi TACHI ,  Ryota NIHEI ,  Yoshikazu HOSOMURA

IPC: H10B80/00 ,  H01L23/00 ,  H01L23/50

CPC classification number: H10B80/00 ,  H01L23/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/48 ,  H01L24/80 ,  H01L24/06 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/48463 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes a metal layer disposed above a transistor on a first substrate. The metal layer includes a first region extending in a first direction and a second region that has a width in the first direction smaller than the first region and protrudes from the first region in a second direction, and has a first corner portion having an angle larger than 180° as viewed in a third direction between a proximal end portion of the second region and the first region. The metal layer includes a first portion that is disposed within the first region and has a lower surface at a first height, and a second portion that is disposed within the second region and has a lower surface at a second height lower than the first height. A step present at a boundary between the first portion and the second portion is disposed away from an edge of the second region at a first position near the first corner portion in the second direction and adjacent to the edge of the second region at a second position away from the first corner portion than the first position.

公开(公告)号：US20210125673A1

公开(公告)日：2021-04-29

申请号：US17007896

申请日：2020-08-31

Applicant: Kioxia Corporation

Inventor： Kiichi TACHI ,  Takashi HIROTANI

IPC: G11C16/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

Abstract: A semiconductor storage device includes a bit line driver, and a control circuit configured to be able to execute a writing sequence for repeating at least one loop including a program operation for writing data into at least one of the plurality of memory cells and a verify operation for verifying the data a plurality of times while increasing a program voltage by a step-up voltage. The bit line driver can obtain a number of memory cells into which writing is completed or a number of memory cells into which writing is insufficient for each of the at least two consecutive loops from a result of the verify operation, and the control circuit can determine the step-up voltage in the subsequent loop based on a result obtained by the bit line driver.

公开(公告)号：US20240321363A1

公开(公告)日：2024-09-26

申请号：US18586360

申请日：2024-02-23

Applicant: Kioxia Corporation

Inventor： Kiichi TACHI

IPC: G11C16/26 ,  G11C5/06 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: G11C16/26 ,  G11C5/06 ,  G11C16/0483 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor memory device includes conductive layers stacked in a stacking direction and extending in a first direction intersecting the stacking direction, semiconductor columns extending in the stacking direction and facing the conductive layers, charge storage films provided between the conductive layers and the semiconductor columns, first and second wirings provided on one side in the stacking direction with respect to the conductive layers, arranged in the first direction, and electrically connected to the semiconductor columns, sense amplifier units electrically connected to the first wirings, and a node electrically and commonly connected to the second wirings. One of the sense amplifier units is electrically connected to K1 number of first wirings (where K1 is an integer of 1 or more). The node is electrically connected to K number of second wirings (where K2 is an integer of 2 or more and is greater than K1).

公开(公告)号：US20220262720A1

公开(公告)日：2022-08-18

申请号：US17403678

申请日：2021-08-16

Applicant: KIOXIA CORPORATION

Inventor： Kiichi TACHI

IPC: H01L23/528 ,  H01L27/11582

Abstract: A semiconductor storage device includes a first stacked region, a second stacked region, and a connection region arranged between the first and second stacked regions. In the connection region, one of a plurality of conductor layers in an upper stepped portion is connected to one of the plurality of conductor layers in the first stacked region via one of the plurality of conductor layers in a bridge portion.