公开(公告)号：US20230371406A1

公开(公告)日：2023-11-16

申请号：US18353908

申请日：2023-07-18

Applicant: Kioxia Corporation

Inventor： Tomohito KAWASHIMA ,  Takahiro NONAKA ,  Yusuke ARAYASHIKI ,  Takayuki ISHIKAWA

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/826 ,  H10N70/011 ,  H10N70/24 ,  H10N70/245 ,  H10N70/841 ,  H10N70/8416 ,  H10N70/8833 ,  H10B63/84

Abstract: A memory device, containing a first interconnection extending in a first direction; a first layer including tungsten nitride provided on the first interconnection; a stacked body layer provided on the first layer, a second layer including tungsten provided on the stacked body layer, a memory cell including a germanium tellurium antimony provided on the second layer, a second interconnection provided above the memory cell and extending in a second direction intersecting the first direction; and a third layer including tungsten disposed between the memory cell and the second interconnection, wherein the stacked body layer contains a first material layer of a first material which is different from a material of the first layer, and a second material layer including a second material which is different from the first material and the material of the first layer, wherein the second layer covers a lower surface of the memory cell, and wherein the third layer covers an upper surface of the memory cell.

公开(公告)号：US20220085058A1

公开(公告)日：2022-03-17

申请号：US17190871

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Yosuke MURAKAMI ,  Satoshi NAGASHIMA ,  Nobuyuki MOMO ,  Takayuki ISHIKAWA ,  Yusuke ARAYASHIKI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L23/00 ,  H01L27/11524 ,  H01L27/1157 ,  G11C7/18

Abstract: A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

公开(公告)号：US20220310646A1

公开(公告)日：2022-09-29

申请号：US17460944

申请日：2021-08-30

Applicant: Kioxia Corporation

Inventor： Yusuke ARAYASHIKI

IPC: H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor storage device includes a third semiconductor layer and a fourth semiconductor layer. The third semiconductor layer has a first width; the third semiconductor layer and a first insulating layer are disposed apart with a first distance; the third semiconductor layer and a second insulating layer are disposed apart with a second distance; the fourth semiconductor layer has a second width; the fourth semiconductor layer and the first insulating layer are disposed apart with a third distance; and the fourth semiconductor layer and the second insulating layer are disposed apart with a fourth distance. A shorter one of the first distance and the second distance is shorter than a shorter one of the third distance and the fourth distance, and the first width is larger than the second width.

公开(公告)号：US20230253029A1

公开(公告)日：2023-08-10

申请号：US17842516

申请日：2022-06-16

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Kikuko SUGIMAE ,  Katsuya NISHIYAMA ,  Yusuke ARAYASHIKI ,  Motohiko FUJIMATSU ,  Kyosuke SANO ,  Noboru SHIBATA

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/06

CPC classification number: G11C11/4085 ,  G11C11/4074 ,  G11C11/4099 ,  G11C5/063

Abstract: According to an embodiment, a circuit in a semiconductor memory device sets threshold voltages of a plurality of memory cells such that two first distributions are formed in a first section on a lowest voltage side in 2N sections. After that, the circuit sets threshold voltages of the plurality of memory cells such that 2(1+M) second distributions are separately formed two by two. The circuit then sets 2N third distributions for the 2N sections.

公开(公告)号：US20230024213A1

公开(公告)日：2023-01-26

申请号：US17960660

申请日：2022-10-05

Applicant: Kioxia Corporation

Inventor： Kikuko SUGIMAE ,  Yusuke ARAYASHIKI

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.

公开(公告)号：US20250124989A1

公开(公告)日：2025-04-17

申请号：US18814679

申请日：2024-08-26

Applicant: Kioxia Corporation

Inventor： Akiyuki MURAYAMA ,  Yusuke ARAYASHIKI ,  Tsuyoshi OGIKUBO ,  Suzuka KAJIWARA ,  Motohiko FUJIMATSU ,  Katsuya NISHIYAMA ,  Kikuko SUGIMAE

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of bit lines, a source line, a plurality of NAND strings, a first and a second sub block, a first word line group included in the first sub block, a second word line group included in the second sub block, and a dummy word line located between the first and second sub blocks; and a control circuit capable of applying predetermined voltages to the first word line group, the second word line group, and the dummy word line. When a specific word line belonging to the first word line group is selected for the execution of a write operation, a voltage higher than voltages applied to an unselected word line belonging to the first word line group and the second word line group is applied to the dummy word line.

公开(公告)号：US20210296332A1

公开(公告)日：2021-09-23

申请号：US17010776

申请日：2020-09-02

Applicant: KIOXIA CORPORATION

Inventor： Yefei HAN ,  Yusuke ARAYASHIKI

IPC: H01L27/11521 ,  H01L27/11519 ,  H01L23/00

Abstract: A semiconductor memory device includes a semiconductor pillar including a semiconductor layer and extending along a first direction, a first wiring extending along a second direction crossing the first direction, a first electrode between the semiconductor pillar and the first wiring, a first insulating layer between the first electrode and the first wiring and adjacent to the first electrode, a second insulating layer between the first insulating layer and the first wiring and adjacent to the first insulating layer, the second insulating layer having a higher dielectric constant than the first insulating layer, and a third insulating layer between the second insulating layer and the first wiring. A shortest distance between the second insulating layer and the semiconductor layer in the second direction is greater than a shortest distance between the first electrode and the semiconductor layer in the second direction.

公开(公告)号：US20240265984A1

公开(公告)日：2024-08-08

申请号：US18432269

申请日：2024-02-05

Applicant: Kioxia Corporation

Inventor： Noboru SHIBATA ,  Kikuko SUGIMAE ,  Yusuke ARAYASHIKI ,  Katsuya NISHIYAMA ,  Motohiko FUJIMATSU ,  Akiyuki MURAYAMA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/26

Abstract: According to one embodiment, a memory device includes a first memory cell and a sequencer. The first memory cell is configured to store multi-bit data with a k-value threshold voltage level (k is an integer of 2 or larger). The sequencer is configured to execute a write operation having a loop process including a program operation and a verify operation. The program operation includes a first program process and a second program process. The sequencer is further configured to cause the first memory cell to store data by either the first program process or the second program process according to data to be written into the first memory cell in the write operation.

公开(公告)号：US20230402395A1

公开(公告)日：2023-12-14

申请号：US18331519

申请日：2023-06-08

Applicant: Kioxia Corporation

Inventor： Kotaro NODA ,  Kyoko NODA ,  Shosuke FUJII ,  Yusuke ARAYASHIKI ,  Hiroyuki ODE

IPC: H01L23/544 ,  H10B63/10 ,  H10B63/00

CPC classification number: H01L23/544 ,  H10B63/10 ,  H10B63/24 ,  H10B63/80 ,  H01L2223/54426

Abstract: A semiconductor device includes: a semiconductor substrate including a first area and a second area; a plurality of memory cells provided in the first area; a mark provided in the second area and having a first side surface and a second side surface that intersects with the first side surface; and a plurality of patterns provided in the second area and provided on the first side surface and the second side surface.