公开(公告)号：US5729039A

公开(公告)日：1998-03-17

申请号：US642834

申请日：1996-05-03

申请人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

发明人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/12

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

摘要： An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

摘要翻译： SOI晶体管具有通过到门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免了将源连接到身体的需要，如通过身体的现有技术方案 通过来源联系。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。

公开(公告)号：US5962895A

公开(公告)日：1999-10-05

申请号：US336956

申请日：1994-11-10

申请人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

发明人： Klaus Dietrich Beyer ,  Taqi Nasser Buti ,  Chang-Ming Hsieh ,  Louis Lu-Chen Hsu

IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/01

CPC分类号： H01L29/66772 ,  H01L29/41783 ,  H01L29/78612 ,  Y10S148/15

摘要： SOI Transistor Having a Self-aligned Body Contact An SOI transistor has a self-aligned body contact formed through an extension to the gate, thereby forming the body contact with minimal increase in area and also avoiding the need to tie the source to the body, as in prior art schemes that passed the body contact through the source. The body contact aperture is formed by raising the source and drain to define an initial aperture, depositing a conformal layer that is etched to create aperture-defining sidewalls and etching the contact aperture using these sidewalls to define sidewall support members that support insulating sidewalls to isolate the collection electrode from both the gate and from the source and drain.

摘要翻译： 具有自对准体接触的SOI晶体管SOI晶体管具有通过到门的延伸形成的自对准体接触，从而以最小的面积增加形成身体接触，并且还避免将源与身体相关联， 如通过身体接触通过源的现有技术方案中那样。 身体接触孔通过提高源极和漏极以形成初始孔径而形成，沉积被蚀刻以形成孔限定侧壁的共形层并且使用这些侧壁蚀刻接触孔以限定支撑绝缘侧壁以隔离的侧壁支撑构件 收集电极来自闸门和源极和漏极。

公开(公告)号：US5965459A

公开(公告)日：1999-10-12

申请号：US729558

申请日：1996-10-11

申请人： Klaus Dietrich Beyer

发明人： Klaus Dietrich Beyer

IPC分类号： H01L21/3105 ,  H01L21/00 ,  H01L21/70

CPC分类号： H01L21/31053 ,  Y10S438/959

摘要： A planarizing method involves a first polishing step in which a relatively hard, low compressibility pad removes excess material of a first layer and planarizes the first layer. Deep defects emanating from the polishing surface formed during the first polishing step are then enlarged and filled with a second layer. After filling, and optionally annealing, the second layer is planarized by polishing with a relatively soft and high compressibility pad or by anisotropic etching.

摘要翻译： 平面化方法包括第一抛光步骤，其中相对较硬的低压缩性垫移除第一层的多余材料并使第一层平坦化。 然后，从第一研磨步骤中形成的抛光表面发出的深度缺陷被扩大并填充第二层。 在填充和任选退火之后，通过用相对柔软和高压缩性垫或通过各向异性蚀刻进行抛光来平坦化第二层。

公开(公告)号：US4110125A

公开(公告)日：1978-08-29

申请号：US773885

申请日：1977-03-03

申请人： Klaus Dietrich Beyer

发明人： Klaus Dietrich Beyer

IPC分类号： H01L21/033 ,  H01L21/314 ,  H01L29/08 ,  H01L21/95 ,  H01L21/74 ,  H01L21/76

CPC分类号： H01L29/0804 ,  H01L21/033 ,  H01L21/3144 ,  Y10S148/003 ,  Y10S148/033 ,  Y10S148/043 ,  Y10S148/085 ,  Y10S148/117 ,  Y10S148/131

摘要： A method for fabricating microminiature, planar semiconductor devices in which the number of defects, in particular, pipes, is minimized. The thicknesses of the thermally grown silicon dioxide and of the silicon nitride masking layers which are used for the formation of limited impurity regions by high temperature diffusion processes within the semiconductor substrate have a specified, limited range. The thickness of the silicon dioxide is between 800A - 3000A and the thickness of the silicon nitride is between around 250A and 600A, preferably 500A. The method is particularly useful in forming extremely small emitter regions in bipolar transistors.

摘要翻译： 一种制造微型平面半导体器件的方法，其中缺陷数量，特别是管道的数量最小化。 用于通过半导体衬底内的高温扩散工艺形成有限杂质区域的热生长二氧化硅和氮化硅掩蔽层的厚度具有规定的有限范围。 二氧化硅的厚度在800A至3000A之间，氮化硅的厚度在约250A至600A之间，优选为500A。 该方法在双极晶体管中形成极小的发射极区域特别有用。

公开(公告)号：US07183175B2

公开(公告)日：2007-02-27

申请号：US11172707

申请日：2005-07-01

申请人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

发明人： Steven John Koester ,  Klaus Dietrich Beyer ,  Michael John Hargrove ,  Kern Rim ,  Kevin Kok Chan

IPC分类号： H01L21/762

CPC分类号： H01L29/7842 ,  H01L21/76224 ,  H01L29/78687

摘要： A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

摘要翻译： 公开了用于隔离电子设备的结构和用于制造该结构的方法。 电子器件在包括在应变Si层下面的基于SiGe的层的衬底中被处理。 隔离结构包括从衬底顶表面向下延伸并且穿透到基于SiGe的层中的沟槽，在衬底中形成侧壁。 外延Si衬垫选择性地沉积在沟槽侧壁上，随后被热氧化。 沟槽填充有沟槽电介质，其在衬底顶表面上方突出。