公开(公告)号：US20100265765A1

公开(公告)日：2010-10-21

申请号：US12662431

申请日：2010-04-16

Applicant: Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

Inventor： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

IPC: G11C16/02 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/24

Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Abstract translation: 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

公开(公告)号：USD606813S1

公开(公告)日：2009-12-29

申请号：US29335057

申请日：2009-04-08

Applicant: Kwang-Tae Kim

Designer： Kwang-Tae Kim

公开(公告)号：US07863110B2

公开(公告)日：2011-01-04

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L21/332 ,  H01L31/119 ,  H01L23/58

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：USD610878S1

公开(公告)日：2010-03-02

申请号：US29337809

申请日：2009-05-29

Applicant: Kwang-Tae Kim

Designer： Kwang-Tae Kim

公开(公告)号：US20080093701A1

公开(公告)日：2008-04-24

申请号：US11907994

申请日：2007-10-19

Applicant: Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

Inventor： Tea-Kwang Yu ,  Kong-Sam Jang ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Eun-Mi Hong

IPC: H01L29/00 ,  H01L21/761

CPC classification number: H01L29/861 ,  H01L21/76224 ,  H01L27/105 ,  H01L27/1052

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract translation: 半导体器件包括在半导体衬底上限定半导体衬底中的有源区的器件隔离层，在半导体衬底的有源区中具有第一导电类型的低电压阱，第二导电类型的高电压杂质区 半导体衬底的有源区，位于低压阱上部的高电压杂质区，高电压杂质区内的第二导电类型的高浓度杂质区，与器件隔离层间隔开;以及 在器件隔离层和高浓度杂质区之间的第一导电类型的浮置杂质区，浮置杂质区是有源区的上表面的一部分。

公开(公告)号：US07588983B2

公开(公告)日：2009-09-15

申请号：US12012593

申请日：2008-02-04

Applicant: Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

Inventor： Weon-ho Park ,  Byoung-ho Kim ,  Hyun-khe Yoon ,  Seung-beom Yoon ,  Sung-chul Park ,  Ju-ri Kim ,  Kwang-Tae Kim ,  Jeong-wook Han

IPC: H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/11524 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546

Abstract: Provided are an EEPROM cell, an EEPROM device, and methods of manufacturing the EEPROM cell and the EEPROM device. The EEPROM cell is formed on a substrate including a first region and a second region. A first EEPROM device having a first select transistor and a first memory transistor is disposed in the first region, while a second EEPROM device having a second select transistor and a second memory transistor is disposed in the second region. In the first region, a first drain region and a second floating region are formed apart from each other. In the second region, a second drain region and a second floating region are formed apart from each other. A first impurity region, a second impurity region, and a third impurity region are disposed in a common source region between the first and second regions of the substrate. The first and third impurity regions form a DDD structure, and the first and second impurity region form an LDD structure. That is, the first impurity region completely surrounds the second and third impurity regions in horizontal and vertical directions, the second impurity region surrounds the third impurity region in a horizontal direction, and the junction depth of the third impurity is greater than that of the second impurity region.

Abstract translation: 提供了EEPROM单元，EEPROM器件以及EEPROM单元和EEPROM器件的制造方法。 EEPROM单元形成在包括第一区域和第二区域的基板上。 具有第一选择晶体管和第一存储晶体管的第一EEPROM器件设置在第一区域中，而具有第二选择晶体管和第二存储晶体管的第二EEPROM器件设置在第二区域中。 在第一区域中，分开形成第一漏极区域和第二浮动区域。 在第二区域中，第二漏极区域和第二浮动区域彼此分开地形成。 第一杂质区域，第二杂质区域和第三杂质区域设置在基板的第一和第二区域之间的公共源极区域中。 第一和第三杂质区形成DDD结构，第一和第二杂质区形成LDD结构。 也就是说，第一杂质区域在水平和垂直方向上完全围绕第二和第三杂质区域，第二杂质区域在水平方向上包围第三杂质区域，并且第三杂质的结深度大于第二杂质区域的结深度 杂质区。

公开(公告)号：US07429511B2

公开(公告)日：2008-09-30

申请号：US11171706

申请日：2005-06-30

Applicant: Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

Inventor： Weon-Ho Park ,  Tea-Kwang Yu ,  Kyoung-Hwan Kim ,  Kwang-Tae Kim

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  G11C16/0433 ,  H01L27/11524

Abstract: A method of forming a tunneling insulating layer having a size smaller than the size obtained by the resolution of a photolithography process is provided. The method includes the steps of forming a first insulating layer and a second insulating layer on a substrate, forming a re-flowable material layer pattern to re-flow the re-flowable material layer pattern, removing the second insulating layer and the first insulating layer to expose the substrate, and forming a tunneling insulating layer.

Abstract translation: 提供一种形成尺寸小于通过光刻工艺的分辨率获得的尺寸的隧道绝缘层的方法。 该方法包括在基板上形成第一绝缘层和第二绝缘层的步骤，形成可再流动的材料层图案以再流动可再流动的材料层图案，去除第二绝缘层和第一绝缘层 露出基板，形成隧道绝缘层。

公开(公告)号：US5302459A

公开(公告)日：1994-04-12

申请号：US920710

申请日：1992-07-28

Applicant: Kwang-Tae Kim ,  Ik-Sung Kim ,  Choon-Young Kim

Inventor： Kwang-Tae Kim ,  Ik-Sung Kim ,  Choon-Young Kim

IPC: B29C55/12 ,  B06B1/02 ,  B29C55/02 ,  B29K67/00 ,  B29L7/00 ,  B29L9/00 ,  C08J7/04 ,  C08L83/04 ,  C09D5/00 ,  C09D5/02 ,  C09D133/04 ,  C09D133/06 ,  C09D183/04 ,  C09D183/06 ,  B32B9/04

CPC classification number: C08J7/047 ,  B29C55/026 ,  C09D133/06 ,  B06B2201/56 ,  B29K2067/00 ,  C08J2367/02 ,  C08J2433/00 ,  C08L83/04 ,  Y10T428/31663 ,  Y10T428/31797

Abstract: A method for preparation of a biaxially stretched polyester film with good slip and release properties comprising coating an acrylic resin-based aqueous resin compound, which is derived from adding an amino-modified silicone compound having the structural formula (1), a waxy additive and inert inorganic particles to an acrylic resin, on at least one surface of a mono-axially stretched polyester film, drying the polyester film coated with the aqueous resin compound, mono-axially stretching the dried polyester film in a direction perpendicular to that of the previous mono-axial stretching and heat-treating the stretched polyester film: ##STR1## wherein R' is a hydroxyl group, a methyl or an ethyl; R" is a hydrogen carbide which has 0 to 10 carbon atoms and to which NH or NH.sub.2 is bonded; m is an integer in the range of 5 to 1,000; n is an integer in the range of 100 to 20,000; and n/(m+n)=0.5.

Abstract translation: 一种制备具有良好滑爽和脱模性能的双轴拉伸聚酯薄膜的方法，包括涂布丙烯酸树脂基水性树脂化合物，其衍生自加入具有结构式（1）的氨基改性硅氧烷化合物，蜡状添加剂和 将惰性无机颗粒加入到丙烯酸树脂中，在单轴拉伸聚酯膜的至少一个表面上，干燥涂覆有水性树脂化合物的聚酯膜，沿垂直于先前的方向的方向单轴拉伸干燥的聚酯膜 单轴拉伸和热处理拉伸的聚酯膜：（*化学结构*）（1）其中R'是羟基，甲基或乙基; R“是碳原子数为0〜10并与NH或NH 2键合的碳氢化合物，m为5〜1000的整数，n为100〜20000的整数，n /（ m + n）= 0.5。

公开(公告)号：US08111553B2

公开(公告)日：2012-02-07

申请号：US12662431

申请日：2010-04-16

Applicant: Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

Inventor： Bo-Young Seo ,  Hee-Seog Jeon ,  Kwang-Tae Kim ,  Ji-Hoon Park ,  Myung-Jo Chun

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0433 ,  G11C16/24

Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Abstract translation: 提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。 连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平 在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。 因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

公开(公告)号：US07968405B2

公开(公告)日：2011-06-28

申请号：US12026812

申请日：2008-02-06

Applicant: Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

Inventor： Eun-Mi Hong ,  Kwang-Tae Kim ,  Ji-Hoon Park

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract translation: 提供一种制造非易失性存储器件的方法。 该方法包括在限定活性区域的半导体衬底中形成隔离层并在隔离层上形成模制图案。 第一导电层形成在模制图案的侧壁和顶表面上以及半导体衬底上。 选择性地去除模制图案的顶表面上的第一导电层，形成导电图案。 导电图案包括设置在有源区域上的主体板和从主体板的边缘延伸到模制图案的侧壁上的突起。 然后移除模制图案。 在隔离层和导电图案上形成栅极间电介质层。 还提供了使用该方法制造的非易失性存储器件。