公开(公告)号：US06926770B2

公开(公告)日：2005-08-09

申请号：US10434233

申请日：2003-05-09

申请人： Lung-Han Peng ,  Way-Seen Wang ,  Shu-Mei Tsan ,  Yi-Chun Shih ,  Yung-Chang Zhang ,  Chao-Ching Hsu

发明人： Lung-Han Peng ,  Way-Seen Wang ,  Shu-Mei Tsan ,  Yi-Chun Shih ,  Yung-Chang Zhang ,  Chao-Ching Hsu

IPC分类号： G02F1/37 ,  C30B33/00 ,  G02F1/355 ,  C30B33/06

CPC分类号： G02F1/3558 ,  C30B29/30 ,  C30B33/00

摘要： The present invention relates to a method to control the nucleation and transverse motion of 180° inverted domains in ferroelectric nonlinear crystals. It includes a process composing of a high temperature oxidation of the first metal layer and a pulsed field poling of the second electrodes. The main object of present invention is to provide domain inversion of ferroelectric nonlinear crystals with field control the nucleation and transverse motion of inverted domains and two-dimension nonlinear photonic crystals for time-domain multiple-wave simultaneous lasers and space filter function. Another object of present invention is to provide space-charge effect for screened edge field beneath the metal electrode, The other object of present invention is to provide the constraint of inverted domain nucleation in the oxidized electrode for arbitrarily geometrical form of 2D ferroelectric lattice structure.

摘要翻译： 本发明涉及一种控制铁电非线性晶体中180°倒置畴的成核和横向运动的方法。 它包括构成第一金属层的高温氧化和第二电极的脉冲场极化的工艺。 本发明的主要目的是提供铁电非线性晶体的域反转，其中场控制反向域的成核和横向运动以及用于时域多波同时激光器和空间滤波器功能的二维非线性光子晶体。 本发明的另一个目的是为金属电极下方的筛选边缘场提供空间电荷效应。本发明的另一个目的是提供二氧化铁电晶格结构的任意几何形式的氧化电极中的反向晶核成核的约束。

公开(公告)号：US20140277812A1

公开(公告)日：2014-09-18

申请号：US13801777

申请日：2013-03-13

申请人： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

发明人： Yi-Chun Shih ,  Kaushik Mazumdar ,  Stephen T. Kim ,  Rinkle Jain ,  James W. Tschanz ,  Muhammad M. Khellah

IPC分类号： G05F5/00

CPC分类号： G05F1/563 ,  G05F1/00 ,  G05F1/46 ,  H02M3/156

摘要： Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

摘要翻译： 描述了一种装置，其包括：耦合到输入电源和负载的多个晶体管; 第一比较器，其具有耦合到所述负载的第一节点，以及耦合到第一参考的第二节点; 第二比较器，其具有耦合到所述负载的第一节点，以及耦合到第二参考的第二节点，所述第二参考与所述第一参考不同; 以及逻辑单元，用于接收第一比较器的输出和第二比较器的输出，逻辑单元根据第一和第二比较器的输出接通或关断多个晶体管的晶体管。

公开(公告)号：US08541278B2

公开(公告)日：2013-09-24

申请号：US13234132

申请日：2011-09-15

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

公开(公告)号：US20090034207A1

公开(公告)日：2009-02-05

申请号：US11831457

申请日：2007-07-31

申请人： Lin-Wei Chang ,  Yi-Chun Shih

发明人： Lin-Wei Chang ,  Yi-Chun Shih

IPC分类号： H05K5/00

CPC分类号： H05K7/1427 ,  G06F1/184

摘要： A casing including a carrying frame and at least one detachable carrying component is provided. The carrying frame includes two sidewalls and a base. The sidewalls face each other, and each sidewall has a first sliding connection portion. The sidewalls are respectively connected to the base, and the sidewalls and the base form an accommodating space. The detachable carrying component has two second sliding connection portions, and the second sliding connection portions are suitable for being slidingly connected to the first sliding connection portions respectively. The detachable carrying component is suitable for being slidingly disposed in the accommodating space along a gravitational direction. The method of assembling the casing is simpler.

摘要翻译： 提供了一种包括承载框架和至少一个可拆卸承载部件的壳体。 承载框架包括两个侧壁和底座。 侧壁彼此面对，并且每个侧壁具有第一滑动连接部分。 侧壁分别连接到基部，并且侧壁和基部形成容纳空间。 可拆卸的承载部件具有两个第二滑动连接部分，并且第二滑动连接部分分别适于滑动地连接到第一滑动连接部分。 可拆卸的承载部件适于沿着重力方向滑动地设置在容纳空间中。 组装外壳的方法更简单。

公开(公告)号：US20080113607A1

公开(公告)日：2008-05-15

申请号：US11540314

申请日：2006-09-28

申请人： Yi-Chun Shih

发明人： Yi-Chun Shih

IPC分类号： F24F1/00

CPC分类号： G06F1/20 ,  H05K7/20727

摘要： A wind-guiding cover is applicable to an electronic apparatus having a dissipating fan, a first heat-generating device and a second heat-generating device sequentially disposed along a straight line. The electronic apparatus further includes an upper lid. The wind-guiding cover includes a cover board for covering the first heat-generating device, and a plurality of side boards disposed on two sides of the cover board. The cover board is formed with a wind-guiding opening corresponding in position to the first heat-generating device. The side boards and the cover board form a first passageway. The wind-guiding opening and the upper lid form a second passageway. Therefore, airflow generated from the dissipating fan will be guided through the first passageway to dissipate heat generated from the first heat-generating device, and further through the second passageway to dissipate heat generated from the second heat-generating device.

摘要翻译： 导风罩适用于具有散热风扇的电子设备，沿着直线顺序设置的第一发热装置和第二发热装置。 电子设备还包括上盖。 风导向盖包括用于覆盖第一发热装置的盖板和设置在盖板两侧的多个侧板。 盖板形成有与第一发热装置相对应的导风孔。 侧板和盖板形成第一通道。 导风孔和上盖形成第二通道。 因此，从散热风扇产生的气流将被引导通过第一通道，从而消散从第一发热装置产生的热量，并进一步通过第二通道以散发由第二发热装置产生的热量。

公开(公告)号：US07338300B1

公开(公告)日：2008-03-04

申请号：US11605564

申请日：2006-11-28

申请人： Lin-Wei Chang ,  Yi-Chun Shih

发明人： Lin-Wei Chang ,  Yi-Chun Shih

IPC分类号： H01R12/00

CPC分类号： H01R13/6485 ,  Y10S439/939

摘要： The present invention discloses a static electricity conductive mechanism including a plurality of conductive bumps and conductive members, for conducting static electricity generated by a connector device to a base thereof, the connector device having a connector body disposed on a circuit board, and the base being ground to earth. The conductive bumps of the static electricity conductive mechanism are each disposed on the base. The conductive members are disposed between the connector body and the conductive bumps. The conductive members conduct to the conductive bumps the static electricity generated by the connector body, thus conducting to earth the static electricity generated by the connector body. The prior art involves disposing a resilient element between a connector's body and base and thereby results in poor contact and poor conduction of static electricity between the body and the base. The drawback is solved by the present invention.

摘要翻译： 本发明公开了一种静电导电机构，其包括多个导电凸块和导电构件，用于将由连接器装置产生的静电导入其基部，该连接器装置具有设置在电路板上的连接器主体， 地对地。 静电导电机构的导电凸块各自设置在基座上。 导电构件设置在连接器主体和导电凸块之间。 导电构件对导电凸块传导由连接器主体产生的静电，从而导致由连接器主体产生的静电。 现有技术涉及将弹性元件设置在连接器主体和基座之间，从而导致身体和基座之间的接触不良和静电传导不良。 该缺点由本发明解决。

公开(公告)号：US08890253B2

公开(公告)日：2014-11-18

申请号：US13348961

申请日：2012-01-12

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7808

摘要： A semiconductor device includes: a substrate including a first epitaxial layer that has a first electrical type, and a second epitaxial layer; a transistor that includes a source region and an insulating spacer; an inner surrounding structure including an annular trench and an insulating spacer; an outer surrounding structure that has a second electrical type opposite to the first electrical type, and that is disposed adjacent to an upper surface of the second epitaxial layer to surround and contact the inner surrounding structure; and a conductive structure connecting to the source region, and the inner and outer surrounding structures.

摘要翻译： 半导体器件包括：包括具有第一电型的第一外延层和第二外延层的衬底; 晶体管，其包括源极区域和绝缘间隔物; 包括环形沟槽和绝缘垫片的内部周围结构; 外周围结构具有与第一电气类型相反的第二电气类型，并且邻近第二外延层的上表面设置以围绕和接触内周围结构; 以及连接到源极区域的导电结构以及内部和外部周围结构。

公开(公告)号：US08404531B2

公开(公告)日：2013-03-26

申请号：US13349038

申请日：2012-01-12

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Yi-Chun Shih ,  Main-Gwo Chen

IPC分类号： H01L21/337

CPC分类号： H01L29/7802 ,  H01L21/2253 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/1095

摘要： A method for fabricating a power transistor includes: (a) forming a trench in a substrate with a first electrical type; (b) diffusing second electrical type carriers into the substrate from the trench such that the substrate is formed into a first part and a second part that is diffused with the second electrical type carriers and that adjoins the trench, the first and second parts being crystal lattice continuous to each other; (c) forming a filling portion in the trench, the filling portion adjoining the second part; (d) performing a carrier-implanting process in the second part and the filling portion; and (e) forming over the substrate a gate structure that has a dielectric layer and a conductive layer.

摘要翻译： 一种制造功率晶体管的方法包括：（a）在第一电气类型的衬底中形成沟槽; （b）从沟槽将第二电型载体扩散到衬底中，使得衬底形成为第一部分，第二部分与第二电气型载流子扩散并邻接沟槽，第一和第二部分是晶体 格子相互连续; （c）在所述沟槽中形成填充部分，所述填充部分邻接所述第二部分; （d）在第二部分和填充部分中执行载体植入过程; 和（e）在衬底上形成具有电介质层和导电层的栅极结构。

公开(公告)号：US20120295410A1

公开(公告)日：2012-11-22

申请号：US13234132

申请日：2011-09-15

申请人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

发明人： Yung-Fa Lin ,  Shou-Yi Hsu ,  Meng-Wei Wu ,  Main-Gwo Chen ,  Yi-Chun Shih

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7811 ,  H01L29/7813

摘要： A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.

摘要翻译： 用于制造具有减小的米勒电容的超结半导体功率器件的方法包括以下步骤。 提供了N型衬底，并且在N型衬底上形成P型外延层。 至少在P型外延层中形成沟槽，随后在沟槽的内表面上形成缓冲层。 将N型掺杂剂层填充到沟槽中，然后蚀刻N型掺杂剂层以在沟槽的上部形成凹陷结构。 形成栅极氧化层，同时，N型掺杂剂层中的掺杂剂扩散到P型外延层中，形成N型扩散层。 最后，将栅极导体填充到凹陷结构中，并且在P型外延层中的栅极导体周围形成N型源极掺杂区。

公开(公告)号：US20060133184A1

公开(公告)日：2006-06-22

申请号：US11014258

申请日：2004-12-16

申请人： Jen-Ren Huang ,  Min-Hung Chou ,  Yi-Chun Shih

发明人： Jen-Ren Huang ,  Min-Hung Chou ,  Yi-Chun Shih

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： A plasma damage protection circuit includes a word line driver circuit with plasma damage protection features. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the word line drivers to the semiconductor substrate. Another plasma-based protection circuit includes a device coupled to multiple word line drivers. If, during manufacture, plasma-based processes cause charge to build up on the word lines, the charge passes from the word lines through at least the device to the semiconductor substrate. Thus, these plasma-based protection circuits save space while protecting the integrated circuit from plasma process-based damage.

摘要翻译： 等离子体损伤保护电路包括具有等离子体损伤保护特性的字线驱动电路。 如果在制造期间，基于等离子体的工艺导致电荷在字线上积累，则电荷从字线通过至少字线驱动器到半导体衬底。 另一种基于等离子体的保护电路包括耦合到多个字线驱动器的装置。 如果在制造期间，基于等离子体的工艺导致电荷在字线上积累，则电荷从字线通过至少该器件至半导体衬底。 因此，这些基于等离子体的保护电路节省空间，同时保护集成电路免受基于等离子体处理的损害。