公开(公告)号：US11018155B2

公开(公告)日：2021-05-25

申请号：US16812938

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Charles H. Dennison ,  Gordon A. Haller ,  Merri L. Carlson ,  John D. Hopkins ,  Jia Hui Ng ,  Jie Sun

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L29/792

Abstract: A method of forming a vertical string of memory cells comprises forming a lower stack comprising first alternating tiers comprising vertically-alternating control gate material and insulating material. An upper stack is formed over the lower stack, and comprises second alternating tiers comprising vertically-alternating control gate material and insulating material having an upper opening extending elevationally through multiple of the second alternating tiers. The lower stack comprises a lower opening extending elevationally through multiple of the first alternating tiers and that is occluded by occluding material. At least a portion of the upper opening is elevationally over the occluded lower opening. The occluding material that occludes the lower opening is removed to form an interconnected opening comprising the unoccluded lower opening and the upper opening. Charge storage material is deposited into the interconnected opening for the charge storage structures for the memory cells of the vertical string that are in each of the upper and lower stacks and thereafter tunnel insulator and channel material are formed into the interconnected opening for the memory cells of the vertical string that are in each of the upper and lower stack. Other embodiments are disclosed, including embodiments independent of method.

公开(公告)号：US20190355745A1

公开(公告)日：2019-11-21

申请号：US16528454

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/02 ,  H01L27/115 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US10090317B2

公开(公告)日：2018-10-02

申请号：US15221131

申请日：2016-07-27

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Zhenyu Lu ,  Roger W. Lindsay ,  Brian Cleereman ,  John Hopkins ,  Hongbin Zhu ,  Fatma Arzum Simsek-Ege ,  Prasanna Srinivasan ,  Purnima Narayanan

IPC: H01L21/3205 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04 ,  H01L27/1157

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

公开(公告)号：US09899413B2

公开(公告)日：2018-02-20

申请号：US15472052

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US09634025B2

公开(公告)日：2017-04-25

申请号：US15248968

申请日：2016-08-26

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L21/8242 ,  H01L29/76 ,  H01L27/11582 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US11088168B2

公开(公告)日：2021-08-10

申请号：US16834291

申请日：2020-03-30

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10608004B2

公开(公告)日：2020-03-31

申请号：US16028111

申请日：2018-07-05

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Zhenyu Lu ,  Gordon Haller ,  Jie Sun ,  Randy J. Koval ,  John Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/10 ,  H01L29/51 ,  H01L21/311 ,  H01L27/1157 ,  H01L21/28 ,  H01L29/66

Abstract: Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

公开(公告)号：US10600807B2

公开(公告)日：2020-03-24

申请号：US16528454

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L21/02 ,  H01L21/768 ,  H01L27/11582 ,  H01L21/28 ,  H01L27/115 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20180166464A1

公开(公告)日：2018-06-14

申请号：US15893380

申请日：2018-02-09

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

公开(公告)号：US20170200737A1

公开(公告)日：2017-07-13

申请号：US15472052

申请日：2017-03-28

Applicant: Micron Technology, Inc.

Inventor： Jie Sun ,  Fatma Arzum Simsek-Ege

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11524 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02244 ,  H01L21/02274 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53271 ,  H01L27/115 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.