公开(公告)号：US12183396B2

公开(公告)日：2024-12-31

申请号：US18096072

申请日：2023-01-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures might include a first conductive plate connected to memory cells of a first dummy block of memory cells and to memory cells of a second dummy block of memory cells on opposing sides of a first isolation region; a second conductive plate connected to memory cells of the first dummy block of memory cells and to memory cells of the second dummy block of memory cells on opposing sides of a second isolation region; first and second conductors selectively connected to a first global access line, and connected to the first conductive plate on opposing sides of the first isolation region; third and fourth conductors selectively connected to a second global access line, and connected to the second conductive plate on opposing sides of the second isolation region; and a fifth conductor connected to the third conductor and connected to the second conductor.

公开(公告)号：US12094549B2

公开(公告)日：2024-09-17

申请号：US17889578

申请日：2022-08-17

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Kitae Park

IPC: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

CPC classification number: G11C29/12 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3445 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A system includes a memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including causing an erase operation to be performed. The erase operation includes sub-operations. The operations further include causing defect detection to be performed during at least one sub-operation of the sub-operations. The defect detection is performed using at least one defect detection method with respect to at least one failure point.

公开(公告)号：US11557341B2

公开(公告)日：2023-01-17

申请号：US17011018

申请日：2020-09-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu ,  Paolo Tessariol ,  Tomoko Ogura Iwasaki

IPC: G11C13/00

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.

公开(公告)号：US20220310158A1

公开(公告)日：2022-09-29

申请号：US17301139

申请日：2021-03-26

Applicant: Micron Technology, Inc.

Inventor： Jun Xu

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Control logic in a memory device identifies a set of a plurality of memory cells configured as multi-level cell (MLC) memory to be programmed during a program operation and causes one or more programming pulses to be applied to the set of the plurality of memory cells configured as MLC memory to program memory cells in the set of memory cells configured as MLC memory to respective programming levels of a plurality of programming levels as part of the program operation. Responsive to the one or more programming pulses being applied, the control logic further performs a program verify operation to verify whether the memory cell in the set of memory cells configured as MLC memory were programmed to the respective programming levels of the plurality of programming levels.

公开(公告)号：US20220293182A1

公开(公告)日：2022-09-15

申请号：US17832117

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Huanyou Zhan ,  Massimo Rossini ,  Jun Xu

IPC: G11C16/08 ,  G11C16/04 ,  G01R19/25 ,  G11C16/10 ,  G11C16/26

Abstract: Described are systems and methods for estimating the resistance-capacitance time constant of an electrical circuit (e.g., of a wordline of a memory device). An example system comprises: a memory device comprising a plurality of memory cells electrically coupled to a plurality of wordlines; a resistance-capacitance (RC) measurement circuit to measure a voltage at a specified wordline of the plurality of wordlines; and a processing device coupled to the memory device. The processing device is configured to: apply an initial voltage to a selected wordline of the plurality of wordlines; discharge the selected wordline for a discharge period of time; float the selected wordline until a voltage at the selected wordline is stabilized; determine, by the RC measurement circuit, a stabilized voltage at the selected wordline; and estimate, based on the stabilized voltage, an RC time constant of the wordline.

公开(公告)号：US20220180952A1

公开(公告)日：2022-06-09

申请号：US17115357

申请日：2020-12-08

Applicant: Micron Technology, Inc.

Inventor： Jun Xu ,  Violante Moschiano ,  Erwin E. Yu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/08

Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.

公开(公告)号：US11315641B1

公开(公告)日：2022-04-26

申请号：US17087738

申请日：2020-11-03

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu

IPC: G11C16/26 ,  G11C16/34 ,  H03K19/17728 ,  G11C16/30 ,  G11C16/12

Abstract: Memory might include a controller configured to cause the memory to apply a boost voltage level to each capacitance of a plurality of capacitances each connected to a respective node of a sense circuit, selectively discharge each of the nodes through respective memory cells selected for a sense operation, measure a current demand of the plurality of capacitances while each of the nodes is connected to its respective memory cell, determine a deboost voltage level in response to the measured current demand, apply the deboost voltage level to each capacitance of the plurality of capacitances, and determine a respective data state of each memory cell of the plurality of memory cells while the deboost voltage level is applied to each capacitance of the plurality of capacitances.

公开(公告)号：US20210199703A1

公开(公告)日：2021-07-01

申请号：US16877710

申请日：2020-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Dan Xu ,  Jun Xu ,  Erwin E. Yu

IPC: G01R27/26 ,  G01R27/08 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to determine capacitance and/or resistance values of an access line in response to applying a reference current to the access line, wherein the access line is connected to control gates of memory cells of the array of memory cells.

公开(公告)号：US20210166773A1

公开(公告)日：2021-06-03

申请号：US17078161

申请日：2020-10-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.

公开(公告)号：US20210090670A1

公开(公告)日：2021-03-25

申请号：US17247266

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ke Liang ,  Jun Xu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: Memory might have a controller configured to program a first portion of memory cells of a string of series-connected memory cells closer to a particular end of the string than a second portion of memory cells of the string in an order from a different end of the string to the particular end, and program the second portion of memory cells in an order from the particular end to the different end. Memory might further have a controller configured to increment first and second read counts in response to performing a read operation on a memory cell of a block of memory cells, reset the first read count in response to performing an erase operation on a first portion of the block of memory cells, and reset the second read count in response to performing an erase operation on the second portion of the block of memory cells.