公开(公告)号：US11669265B2

公开(公告)日：2023-06-06

申请号：US17511263

申请日：2021-10-26

Applicant: Micron Technology, Inc.

Inventor： Dhawal Bavishi ,  Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Various embodiments described herein provide for execution of a memory function within a memory sub-system. For example, some embodiments provide for execution of certain memory-related functions internally within the memory sub-system, at the request of a host system, using one or more memory access operations (e.g., direct memory access operations) performed internally within the memory sub-system.

公开(公告)号：US11625197B2

公开(公告)日：2023-04-11

申请号：US17498415

申请日：2021-10-11

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

公开(公告)号：US11567700B2

公开(公告)日：2023-01-31

申请号：US17223684

申请日：2021-04-06

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US11016885B2

公开(公告)日：2021-05-25

申请号：US16285909

申请日：2019-02-26

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker ,  Chandrasekhar Nagarajan

IPC: G06F13/00 ,  G06F13/28 ,  G06F12/06 ,  G06F12/04 ,  G06F9/30

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

公开(公告)号：US10990321B2

公开(公告)日：2021-04-27

申请号：US16280607

申请日：2019-02-20

Applicant: Micron Technology, Inc.

Inventor： Patrick A. La Fratta ,  Robert Walker

IPC: G06F3/06

Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.

公开(公告)号：US20200293438A1

公开(公告)日：2020-09-17

申请号：US16886252

申请日：2020-05-28

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F12/02 ,  G06F3/06 ,  G11C7/04 ,  G06F1/20 ,  G06F1/3234 ,  G06F12/122 ,  G06F13/24 ,  G06F13/16 ,  G06F13/42

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

公开(公告)号：US10042750B2

公开(公告)日：2018-08-07

申请号：US13911797

申请日：2013-06-06

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

公开(公告)号：US20160041785A1

公开(公告)日：2016-02-11

申请号：US14918364

申请日：2015-10-20

Applicant: Micron Technology, Inc.

Inventor： Robert Walker

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0215 ,  G06F12/06 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/161 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/4243 ,  G06F15/7821 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

公开(公告)号：US20140281311A1

公开(公告)日：2014-09-18

申请号：US14055672

申请日：2013-10-16

Applicant: Micron Technology, Inc.

Inventor： Robert Walker ,  David A. Roberts

IPC: G06F3/06

CPC classification number: G06F12/0223 ,  G06F1/206 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673 ,  G06F12/023 ,  G06F12/122 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/4282 ,  G06F2212/1016 ,  G11C7/04 ,  G11C11/40626 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/16

Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.

Abstract translation: 描述了将存储区域映射到基于存储器区域的热数据的处理的方法。 在一些实施例中，存储器控制器可以接收存储器分配请求。 存储器分配请求可以包括逻辑存储器地址。 该方法还可以包括基于存储器系统的存储器区域的热数据将逻辑存储器地址映射到存储器系统的存储器区域中的地址。 还描述了附加的方法和系统。

公开(公告)号：US20140281149A1

公开(公告)日：2014-09-18

申请号：US13911797

申请日：2013-06-06

Applicant: Micron Technology, Inc.

Inventor： David A. Roberts ,  J. Thomas Pawlowski ,  Robert Walker

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/023 ,  G06F12/0292 ,  G06F13/1694 ,  Y02D10/13 ,  Y02D10/14

Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.

Abstract translation: 公开了用于存储器自适应控制的装置和方法。 一个示例性装置包括被配置为运行操作系统的处理单元和耦合到处理单元的存储器。 所述存储器经配置以经由存储器总线与所述处理单元通信。 示例设备还可以包括自适应存储器控制器，其被配置为从存储器和处理单元接收监视的统计数据。 自适应存储器控制器被配置为基于所监视的统计数据来管理存储器。