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公开(公告)号：US10381094B2
公开(公告)日：2019-08-13
申请号：US15290376
申请日：2016-10-11
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chen-Jun Wu , Chih-Chang Hsieh , Tzu-Hsuan Hsu , Hang-Ting Lue
Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i−1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i−1).
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公开(公告)号：US20160012901A1
公开(公告)日：2016-01-14
申请号：US14330106
申请日：2014-07-14
Applicant: Macronix International Co., Ltd.
Inventor： Tzu-Hsuan Hsu , Hang-Ting Lue , Chen-Jun Wu
CPC classification number: G11C16/16 , G11C16/0408 , G11C16/0483 , H01L27/11524 , H01L27/11556 , H01L27/1157
Abstract: A data erase method of a three dimensional (3D) memory device comprising the following steps. First, in a first phase of an erase operation, a first voltage is applied to a first semiconductor channel of the semiconductor channels to erase data stored in the memory cells defined on the first semiconductor channel and a second voltage is applied to a second semiconductor channel of the semiconductor channels, wherein the second semiconductor channel is adjacent to the first semiconductor channel. Then, in a second phase of the erase operation, the second voltage is applied to the first semiconductor channel and the first voltage is applied to the second semiconductor channel.
Abstract translation: 一种三维（3D）存储器件的数据擦除方法，包括以下步骤。 首先，在擦除操作的第一阶段中，将第一电压施加到半导体通道的第一半导体通道，以擦除存储在第一半导体通道上限定的存储单元中的数据，并将第二电压施加到第二半导体通道 的半导体通道，其中第二半导体沟道与第一半导体沟道相邻。 然后，在擦除操作的第二阶段中，将第二电压施加到第一半导体沟道，并将第一电压施加到第二半导体沟道。
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公开(公告)号：US20150372001A1
公开(公告)日：2015-12-24
申请号：US14309923
申请日：2014-06-20
Applicant: Macronix International Co., Ltd.
Inventor： Tzu-Hsuan Hsu , Wei-Chen Chen , Hang-Ting Lue
IPC: H01L27/115 , H01L21/285 , H01L21/768 , H01L21/225 , H01L23/532 , H01L23/528
CPC classification number: H01L21/28525 , H01L21/2257 , H01L23/53271 , H01L27/11578 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer.
Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括在第一电极层和第二电极层之间的第一电极层，第二电极层和电介质层。 第二电极层的宽度在远离电介质层的方向上变大。
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公开(公告)号：US20230215502A1
公开(公告)日：2023-07-06
申请号：US17569424
申请日：2022-01-05
Applicant: MACRONIX International Co., Ltd.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Tzu-Hsuan Hsu
Abstract: A three-dimensional memory device, such as 3D AND Flash memory device, includes a first page buffer, a second page buffer, a sense amplifier, a first path selector, and a second path selector. The first page buffer and the second page buffer are respectively configured to temporarily store a first write-in data and a second write-in data. The first path selector couples the sense amplifier or the first page buffer to a first global bit line according to a first control signal. The second path selector couples the sense amplifier or the second page buffer to a second global bit line according to a second control signal.
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公开(公告)号：US09252155B2
公开(公告)日：2016-02-02
申请号：US14309923
申请日：2014-06-20
Applicant: Macronix International Co., Ltd.
Inventor： Tzu-Hsuan Hsu , Wei-Chen Chen , Hang-Ting Lue
IPC: H01L23/52 , H01L27/115 , H01L23/532 , H01L23/528 , H01L21/768 , H01L21/225 , H01L21/285
CPC classification number: H01L21/28525 , H01L21/2257 , H01L23/53271 , H01L27/11578 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a first electrode layer, a second electrode layer and a dielectric layer between the first electrode layer and the second electrode layer. A width of the second electrode layer becomes larger in a direction away from the dielectric layer.
Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括在第一电极层和第二电极层之间的第一电极层，第二电极层和电介质层。 第二电极层的宽度在远离电介质层的方向上变大。
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Patent Agency Ranking
公开(公告)号：US12260130B2
公开(公告)日：2025-03-25
申请号：US18161900
申请日：2023-01-31
Applicant: MACRONIX International Co., Ltd.
Inventor： Hang-Ting Lue , Tzu-Hsuan Hsu , Teng-Hao Yeh , Chih-Chang Hsieh , Chun-Hsiung Hung , Yung-Chun Li
IPC: G06F17/16 , G06F3/06 , G06F7/49 , G06N3/00 , G11C7/06 , G11C7/10 , G11C7/18 , G11C8/14 , G11C16/04 , G11C16/24 , G11C16/28 , G11C27/00
Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.
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公开(公告)号：US20240170076A1
公开(公告)日：2024-05-23
申请号：US17988773
申请日：2022-11-17
Applicant: MACRONIX International Co., Ltd.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Tzu-Hsuan Hsu , Chen-Huan Chen , Ken-Hui Chen
CPC classification number: G11C16/3459 , G11C7/1039 , G11C16/08 , G11C16/24
Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
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公开(公告)号：US11221827B1
公开(公告)日：2022-01-11
申请号：US17006493
申请日：2020-08-28
Applicant: MACRONIX International Co., Ltd.
Inventor： Po-Kai Hsu , Teng-Hao Yeh , Tzu-Hsuan Hsu , Hang-Ting Lue
Abstract: An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
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公开(公告)号：US12198770B2
公开(公告)日：2025-01-14
申请号：US17988773
申请日：2022-11-17
Applicant: MACRONIX International Co., Ltd.
Inventor： Teng-Hao Yeh , Hang-Ting Lue , Tzu-Hsuan Hsu , Chen-Huan Chen , Ken-Hui Chen
Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.
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公开(公告)号：US11430527B1
公开(公告)日：2022-08-30
申请号：US17233590
申请日：2021-04-19
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Hang-Ting Lue , Tzu-Hsuan Hsu
Abstract: A method for performing an operation in a memory device is provided. The method includes the following steps. An erasing operation is performed on one selected word line of the memory device to ensure that a plurality of first cells to be programed and a plurality of second cells to be erased connected to the selected word line have threshold voltages lower than a first predetermined level. A programming operation is performed on the selected word line, such that the first cells are suffered a first program bias and the second cells are suffered a second program bias which is lower than the first program bias.
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