公开(公告)号：US12277965B2

公开(公告)日：2025-04-15

申请号：US18319513

申请日：2023-05-18

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: G11C11/00 ,  G11C11/4067 ,  G11C11/4097 ,  H10B12/10

Abstract: A memory structure and methods for operating memory structures are provided. The memory structure includes a first, a second and a third gate structures disposed along a first direction and separated from each other, channel bodies having first ends and second ends, source regions separated from each other, having first conductivity types and connected to the first ends of the channel bodies respectively, drain regions separated from each other, having second conductivity types and connected to the second ends of the channel bodies respectively, and first side plugs disposed along a second direction, extending along a third direction, and electrically connected to the source regions and the channel bodies. The first gate structure includes island structures disposed along the second direction and extending along the third direction.

公开(公告)号：US12254915B1

公开(公告)日：2025-03-18

申请号：US18240852

申请日：2023-08-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Dai-Ying Lee ,  Teng-Hao Yeh ,  Wei-Chen Chen ,  Rachit Dobhal ,  Zefu Zhao ,  Chee-Wee Liu

IPC: G11C11/22 ,  G11C5/06 ,  H10B51/20 ,  H10D30/01 ,  H10D30/69

Abstract: The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.

公开(公告)号：US20230413552A1

公开(公告)日：2023-12-21

申请号：US17845601

申请日：2022-06-21

Applicant: MACRONIX International Co., Ltd.

Inventor： Hang-Ting Lue ,  Teng Hao Yeh ,  Cheng-Yu Lee ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L23/535

Abstract: A three-dimensional flash memory device may be a AND flash memory device. The three-dimensional flash memory device includes: a substrate, a gate stack structure, a plurality of slit structures, a plurality of memory arrays, and a plurality of conductive pillars. The gate stack structure is located above the substrate. The plurality of slit structures extend through the gate stack structure and divide the gate stack structure into a plurality of blocks. The plurality of memory arrays are disposed in the gate stack structure of the plurality of blocks. The plurality of conductive pillars extends through the gate stack structure in the plurality of blocks, and disposed between the plurality of memory arrays and between the plurality of slit structures.

公开(公告)号：US09287406B2

公开(公告)日：2016-03-15

申请号：US14163639

申请日：2014-01-24

Applicant: Macronix International Co., Ltd.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/739 ,  H01L29/423 ,  H01L27/092 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/115

CPC classification number: H01L29/78645 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/092 ,  H01L27/11568 ,  H01L29/4232 ,  H01L29/66484 ,  H01L29/7391

Abstract: A dual-mode transistor structure comprises a semiconductor body. The semiconductor body of the device includes a channel region, a p-type terminal region (operable as a source or drain) adjacent a first side of the channel region and an n-type terminal region (operable as a source or drain) adjacent a second side of the channel region. A gate insulator is disposed on a surface of the semiconductor body over the channel region. A gate is disposed on the gate insulator over the channel region. A first assist gate is disposed on a first side of the gate, and a second assist gate is disposed on a second side of the gate. Optionally, a back gate can be included beneath the channel region. Biasing the assist gates can be used to select n-channel or p-channel modes in a single device.

Abstract translation: 双模式晶体管结构包括半导体本体。 器件的半导体本体包括与沟道区的第一侧相邻的沟道区，p型端子区（可操作为源极或漏极）和邻近沟道区的n型端子区域（可用作源极或漏极） 通道区域的第二侧。 栅极绝缘体设置在沟道区域上的半导体本体的表面上。 栅极设置在沟道区域上的栅极绝缘体上。 第一辅助栅极设置在栅极的第一侧上，第二辅助栅极设置在栅极的第二侧上。 可选地，可以在通道区域下面包括后门。 可以使用偏置辅助栅极在单个器件中选择n沟道或p沟道模式。

公开(公告)号：US11968833B2

公开(公告)日：2024-04-23

申请号：US17149782

申请日：2021-01-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: H10B43/27 ,  H01L29/10 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/1037 ,  H10B43/10 ,  H10B43/35

Abstract: A memory device includes a source element, a drain element, channel layers, control electrode layers, and a memory layer. The channel layers are individually electrically connected between the source element and the drain element. Memory cells are defined in the memory layer between the control electrode layers and the channel layers.

公开(公告)号：US11765901B2

公开(公告)日：2023-09-19

申请号：US17488128

申请日：2021-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: G11C16/10 ,  H10B43/27 ,  G11C16/26 ,  G11C16/16 ,  H10B41/27

CPC classification number: H10B43/27 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B41/27

Abstract: Disclosed is 3D flash memory comprises a gate stack structure, an annular channel pillar, a first source/drain pillar, a second source/drain pillar and a charge storage structure. The gate stack structure is disposed on a dielectric base, and comprising a plurality of gate layers electrically insulated from each other. The annular channel pillar is disposed on the dielectric base and penetrating through the gate stack structure. The first source/drain pillar and the second source/drain pillar, disposed on the dielectric base, located within the annular channel pillar and penetrating through the gate stack structure, wherein the first source/drain pillar and the second source/drain pillar are separated from each other and are each connected to the annular channel pillar. The charge storage structure is disposed between each of the plurality of gate layers and the annular channel pillar. The first source/drain pillar and the second source/drain pillar are P-type doped.

公开(公告)号：US20190156901A1

公开(公告)日：2019-05-23

申请号：US15818208

申请日：2017-11-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Chen Chen ,  Hang-Ting Lue

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/24

Abstract: A memory device includes a plurality of memory cells arranged in series in a semiconductor body. First and second dummy memory cells arranged in series between a first string select switch and a first edge memory cell at a first end of the plurality of memory cells. The first dummy memory cell is adjacent the first edge memory cell, and the second dummy memory cell is adjacent the first string select switch. A channel line includes channels for the plurality of memory cells and the first and second dummy memory cells. Control circuitry is adapted for programming a selected memory cell in the plurality of memory cells corresponding to a selected word line by applying a switching voltage to the first dummy memory cell, the switching voltage having a first voltage level during a first time interval, and thereafter changing to a second voltage level higher than the first voltage level.

公开(公告)号：US10141328B2

公开(公告)日：2018-11-27

申请号：US15379527

申请日：2016-12-15

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting Lue ,  Wei-Chen Chen

IPC: H01L27/11582 ,  H01L21/02

Abstract: A 3D memory device includes a substrate, a ridge-shaped stack, a memory layer, a channel layer and a capping layer. The ridge-shaped stack includes a plurality of conductive strips extending along a first direction and stacked on the substrate. The memory layer is stacked on a vertical sidewall of the ridge-shaped stack along a second direction that forms a non-straight with the first direction. The channel layer is stacked on the memory layer along the second direction and has a narrow sidewall having a long side extending along the first direction. The capping layer is stacked on the narrow sidewall along a third direction that forms a non-straight angle with the second direction.

公开(公告)号：US09536893B2

公开(公告)日：2017-01-03

申请号：US14541169

申请日：2014-11-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yi-Hsuan Hsiao ,  Wei-Chen Chen

IPC: H01L21/283 ,  H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11575

Abstract: A three-dimensional (3D) memory and a method for manufacturing the same are disclosed. According to one embodiment, the 3D memory comprises a thin-film transistor. The thin-film transistor has a source region and a drain region disposed separately. The source region comprises a first source region and a second source region disposed between the first source region and the drain region. The first source region is p-type of doping, the second source region is n-type of doping, and the drain region is n-type of doping.

Abstract translation: 公开了一种三维（3D）存储器及其制造方法。 根据一个实施例，3D存储器包括薄膜晶体管。 薄膜晶体管具有单独设置的源极区域和漏极区域。 源极区域包括设置在第一源极区域和漏极区域之间的第一源极区域和第二源极区域。 第一源区是p型掺杂，第二源区是n型掺杂，漏区是n型掺杂。

公开(公告)号：US09484353B1

公开(公告)日：2016-11-01

申请号：US14803218

申请日：2015-07-20

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Erh-Kun Lai ,  Wei-Chen Chen ,  Dai-Ying Lee

IPC: H01L27/115 ,  H01L21/02 ,  H01L29/788 ,  H01L21/28 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11556 ,  H01L21/02164 ,  H01L21/0223 ,  H01L21/28273 ,  H01L29/04 ,  H01L29/16 ,  H01L29/7889

Abstract: A memory device includes a first insulating layer, a second insulating layer, an isolation layer, a floating gate electrode, a control gate electrode, a channel layer and a tunneling oxide layer. The second insulating layer is disposed adjacent to and substantially parallel with the first insulating layer to form an interlayer space there between. The isolation layer is disposed in the interlayer space to form a non-straight angle with the first insulating layer, and divides the interlayer space into a first recess and a second recess. The floating gate electrode is disposed in the first recess. The control gate electrode is disposed in the second recess. The channel layer is disposed on an opening surface of the first recess and forms a non-straight angle with the first insulating layer. The tunneling oxide layer is disposed between the channel layer and the floating gate electrode.

Abstract translation: 存储器件包括第一绝缘层，第二绝缘层，隔离层，浮栅电极，控制栅电极，沟道层和隧道氧化物层。 第二绝缘层设置成与第一绝缘层相邻并基本上平行，以在其之间形成层间空间。 隔离层设置在层间空间中以与第一绝缘层形成非直角，并且将层间空间划分成第一凹部和第二凹部。 浮栅电极设置在第一凹槽中。 控制栅电极设置在第二凹槽中。 沟道层设置在第一凹部的开口表面上并与第一绝缘层形成非直角。 隧道氧化物层设置在沟道层和浮栅之间。